616 lines
24 KiB
C++
616 lines
24 KiB
C++
/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_H_
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#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_H_
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#include "arch/x86/instruction_set_features_x86.h"
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#include "code_generator.h"
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#include "dex/compiler_enums.h"
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#include "driver/compiler_options.h"
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#include "nodes.h"
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#include "parallel_move_resolver.h"
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#include "utils/x86/assembler_x86.h"
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namespace art {
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namespace x86 {
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// Use a local definition to prevent copying mistakes.
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static constexpr size_t kX86WordSize = kX86PointerSize;
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class CodeGeneratorX86;
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static constexpr Register kParameterCoreRegisters[] = { ECX, EDX, EBX };
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static constexpr RegisterPair kParameterCorePairRegisters[] = { ECX_EDX, EDX_EBX };
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static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
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static constexpr XmmRegister kParameterFpuRegisters[] = { XMM0, XMM1, XMM2, XMM3 };
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static constexpr size_t kParameterFpuRegistersLength = arraysize(kParameterFpuRegisters);
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static constexpr Register kRuntimeParameterCoreRegisters[] = { EAX, ECX, EDX, EBX };
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static constexpr size_t kRuntimeParameterCoreRegistersLength =
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arraysize(kRuntimeParameterCoreRegisters);
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static constexpr XmmRegister kRuntimeParameterFpuRegisters[] = { XMM0, XMM1, XMM2, XMM3 };
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static constexpr size_t kRuntimeParameterFpuRegistersLength =
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arraysize(kRuntimeParameterFpuRegisters);
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class InvokeRuntimeCallingConvention : public CallingConvention<Register, XmmRegister> {
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public:
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InvokeRuntimeCallingConvention()
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: CallingConvention(kRuntimeParameterCoreRegisters,
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kRuntimeParameterCoreRegistersLength,
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kRuntimeParameterFpuRegisters,
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kRuntimeParameterFpuRegistersLength,
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kX86PointerSize) {}
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConvention);
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};
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class InvokeDexCallingConvention : public CallingConvention<Register, XmmRegister> {
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public:
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InvokeDexCallingConvention() : CallingConvention(
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kParameterCoreRegisters,
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kParameterCoreRegistersLength,
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kParameterFpuRegisters,
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kParameterFpuRegistersLength,
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kX86PointerSize) {}
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RegisterPair GetRegisterPairAt(size_t argument_index) {
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DCHECK_LT(argument_index + 1, GetNumberOfRegisters());
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return kParameterCorePairRegisters[argument_index];
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConvention);
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};
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class InvokeDexCallingConventionVisitorX86 : public InvokeDexCallingConventionVisitor {
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public:
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InvokeDexCallingConventionVisitorX86() {}
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virtual ~InvokeDexCallingConventionVisitorX86() {}
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Location GetNextLocation(Primitive::Type type) OVERRIDE;
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Location GetReturnLocation(Primitive::Type type) const OVERRIDE;
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Location GetMethodLocation() const OVERRIDE;
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private:
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InvokeDexCallingConvention calling_convention;
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorX86);
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};
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class FieldAccessCallingConventionX86 : public FieldAccessCallingConvention {
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public:
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FieldAccessCallingConventionX86() {}
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Location GetObjectLocation() const OVERRIDE {
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return Location::RegisterLocation(ECX);
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}
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Location GetFieldIndexLocation() const OVERRIDE {
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return Location::RegisterLocation(EAX);
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}
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Location GetReturnLocation(Primitive::Type type) const OVERRIDE {
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return Primitive::Is64BitType(type)
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? Location::RegisterPairLocation(EAX, EDX)
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: Location::RegisterLocation(EAX);
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}
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Location GetSetValueLocation(Primitive::Type type, bool is_instance) const OVERRIDE {
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return Primitive::Is64BitType(type)
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? Location::RegisterPairLocation(EDX, EBX)
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: (is_instance
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? Location::RegisterLocation(EDX)
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: Location::RegisterLocation(ECX));
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}
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Location GetFpuLocation(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE {
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return Location::FpuRegisterLocation(XMM0);
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionX86);
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};
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class ParallelMoveResolverX86 : public ParallelMoveResolverWithSwap {
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public:
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ParallelMoveResolverX86(ArenaAllocator* allocator, CodeGeneratorX86* codegen)
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: ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {}
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void EmitMove(size_t index) OVERRIDE;
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void EmitSwap(size_t index) OVERRIDE;
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void SpillScratch(int reg) OVERRIDE;
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void RestoreScratch(int reg) OVERRIDE;
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X86Assembler* GetAssembler() const;
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private:
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void Exchange(Register reg, int mem);
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void Exchange(int mem1, int mem2);
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void Exchange32(XmmRegister reg, int mem);
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void MoveMemoryToMemory32(int dst, int src);
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void MoveMemoryToMemory64(int dst, int src);
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CodeGeneratorX86* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverX86);
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};
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class LocationsBuilderX86 : public HGraphVisitor {
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public:
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LocationsBuilderX86(HGraph* graph, CodeGeneratorX86* codegen)
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: HGraphVisitor(graph), codegen_(codegen) {}
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) OVERRIDE;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_X86(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) OVERRIDE {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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private:
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void HandleBitwiseOperation(HBinaryOperation* instruction);
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void HandleInvoke(HInvoke* invoke);
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void HandleCondition(HCondition* condition);
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void HandleShift(HBinaryOperation* instruction);
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void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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CodeGeneratorX86* const codegen_;
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InvokeDexCallingConventionVisitorX86 parameter_visitor_;
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DISALLOW_COPY_AND_ASSIGN(LocationsBuilderX86);
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};
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class InstructionCodeGeneratorX86 : public InstructionCodeGenerator {
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public:
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InstructionCodeGeneratorX86(HGraph* graph, CodeGeneratorX86* codegen);
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) OVERRIDE;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_X86(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) OVERRIDE {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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X86Assembler* GetAssembler() const { return assembler_; }
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// The compare/jump sequence will generate about (1.5 * num_entries) instructions. A jump
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// table version generates 7 instructions and num_entries literals. Compare/jump sequence will
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// generates less code/data with a small num_entries.
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static constexpr uint32_t kPackedSwitchJumpTableThreshold = 5;
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private:
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// Generate code for the given suspend check. If not null, `successor`
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// is the block to branch to if the suspend check is not needed, and after
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// the suspend call.
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void GenerateSuspendCheck(HSuspendCheck* check, HBasicBlock* successor);
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void GenerateClassInitializationCheck(SlowPathCode* slow_path, Register class_reg);
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void HandleBitwiseOperation(HBinaryOperation* instruction);
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void GenerateDivRemIntegral(HBinaryOperation* instruction);
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void DivRemOneOrMinusOne(HBinaryOperation* instruction);
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void DivByPowerOfTwo(HDiv* instruction);
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void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction);
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void GenerateRemFP(HRem* rem);
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void HandleCondition(HCondition* condition);
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void HandleShift(HBinaryOperation* instruction);
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void GenerateShlLong(const Location& loc, Register shifter);
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void GenerateShrLong(const Location& loc, Register shifter);
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void GenerateUShrLong(const Location& loc, Register shifter);
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void GenerateShlLong(const Location& loc, int shift);
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void GenerateShrLong(const Location& loc, int shift);
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void GenerateUShrLong(const Location& loc, int shift);
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void HandleFieldSet(HInstruction* instruction,
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const FieldInfo& field_info,
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bool value_can_be_null);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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// Generate a heap reference load using one register `out`:
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//
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// out <- *(out + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a read barrier and
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// shall be a register in that case; it may be an invalid location
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// otherwise.
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void GenerateReferenceLoadOneRegister(HInstruction* instruction,
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Location out,
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uint32_t offset,
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Location maybe_temp);
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// Generate a heap reference load using two different registers
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// `out` and `obj`:
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//
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// out <- *(obj + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a Baker's (fast
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// path) read barrier and shall be a register in that case; it may
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// be an invalid location otherwise.
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void GenerateReferenceLoadTwoRegisters(HInstruction* instruction,
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Location out,
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Location obj,
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uint32_t offset,
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Location maybe_temp);
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// Generate a GC root reference load:
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//
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// root <- *address
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//
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// while honoring read barriers (if any).
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void GenerateGcRootFieldLoad(HInstruction* instruction,
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Location root,
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const Address& address,
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Label* fixup_label = nullptr);
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// Push value to FPU stack. `is_fp` specifies whether the value is floating point or not.
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// `is_wide` specifies whether it is long/double or not.
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void PushOntoFPStack(Location source, uint32_t temp_offset,
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uint32_t stack_adjustment, bool is_fp, bool is_wide);
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template<class LabelType>
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void GenerateTestAndBranch(HInstruction* instruction,
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size_t condition_input_index,
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LabelType* true_target,
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LabelType* false_target);
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template<class LabelType>
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void GenerateCompareTestAndBranch(HCondition* condition,
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LabelType* true_target,
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LabelType* false_target);
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template<class LabelType>
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void GenerateFPJumps(HCondition* cond, LabelType* true_label, LabelType* false_label);
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template<class LabelType>
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void GenerateLongComparesAndJumps(HCondition* cond,
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LabelType* true_label,
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LabelType* false_label);
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void HandleGoto(HInstruction* got, HBasicBlock* successor);
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void GenPackedSwitchWithCompares(Register value_reg,
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int32_t lower_bound,
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uint32_t num_entries,
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HBasicBlock* switch_block,
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HBasicBlock* default_block);
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void GenerateFPCompare(Location lhs, Location rhs, HInstruction* insn, bool is_double);
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void GenerateIntCompare(Location lhs, Location rhs);
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X86Assembler* const assembler_;
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CodeGeneratorX86* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorX86);
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};
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class JumpTableRIPFixup;
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class CodeGeneratorX86 : public CodeGenerator {
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public:
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CodeGeneratorX86(HGraph* graph,
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const X86InstructionSetFeatures& isa_features,
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const CompilerOptions& compiler_options,
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OptimizingCompilerStats* stats = nullptr);
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virtual ~CodeGeneratorX86() {}
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void GenerateFrameEntry() OVERRIDE;
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void GenerateFrameExit() OVERRIDE;
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void Bind(HBasicBlock* block) OVERRIDE;
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void MoveConstant(Location destination, int32_t value) OVERRIDE;
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void MoveLocation(Location dst, Location src, Primitive::Type dst_type) OVERRIDE;
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void AddLocationAsTemp(Location location, LocationSummary* locations) OVERRIDE;
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size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
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size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
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size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
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size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
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// Generate code to invoke a runtime entry point.
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void InvokeRuntime(QuickEntrypointEnum entrypoint,
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HInstruction* instruction,
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uint32_t dex_pc,
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SlowPathCode* slow_path) OVERRIDE;
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void InvokeRuntime(int32_t entry_point_offset,
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HInstruction* instruction,
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uint32_t dex_pc,
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SlowPathCode* slow_path);
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size_t GetWordSize() const OVERRIDE {
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return kX86WordSize;
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}
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size_t GetFloatingPointSpillSlotSize() const OVERRIDE {
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// 8 bytes == 2 words for each spill.
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return 2 * kX86WordSize;
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}
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HGraphVisitor* GetLocationBuilder() OVERRIDE {
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return &location_builder_;
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}
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HGraphVisitor* GetInstructionVisitor() OVERRIDE {
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return &instruction_visitor_;
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}
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X86Assembler* GetAssembler() OVERRIDE {
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return &assembler_;
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}
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const X86Assembler& GetAssembler() const OVERRIDE {
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return assembler_;
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}
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uintptr_t GetAddressOf(HBasicBlock* block) OVERRIDE {
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return GetLabelOf(block)->Position();
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}
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void SetupBlockedRegisters() const OVERRIDE;
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void DumpCoreRegister(std::ostream& stream, int reg) const OVERRIDE;
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void DumpFloatingPointRegister(std::ostream& stream, int reg) const OVERRIDE;
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// Blocks all register pairs made out of blocked core registers.
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void UpdateBlockedPairRegisters() const;
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ParallelMoveResolverX86* GetMoveResolver() OVERRIDE {
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return &move_resolver_;
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}
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InstructionSet GetInstructionSet() const OVERRIDE {
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return InstructionSet::kX86;
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}
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// Helper method to move a 32bits value between two locations.
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void Move32(Location destination, Location source);
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// Helper method to move a 64bits value between two locations.
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void Move64(Location destination, Location source);
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// Check if the desired_string_load_kind is supported. If it is, return it,
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// otherwise return a fall-back kind that should be used instead.
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HLoadString::LoadKind GetSupportedLoadStringKind(
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HLoadString::LoadKind desired_string_load_kind) OVERRIDE;
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// Check if the desired_dispatch_info is supported. If it is, return it,
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// otherwise return a fall-back info that should be used instead.
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HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch(
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const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info,
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MethodReference target_method) OVERRIDE;
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// Generate a call to a static or direct method.
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void GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, Location temp) OVERRIDE;
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// Generate a call to a virtual method.
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void GenerateVirtualCall(HInvokeVirtual* invoke, Location temp) OVERRIDE;
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void RecordSimplePatch();
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void RecordStringPatch(HLoadString* load_string);
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Label* NewPcRelativeDexCacheArrayPatch(const DexFile& dex_file, uint32_t element_offset);
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void MoveFromReturnRegister(Location trg, Primitive::Type type) OVERRIDE;
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// Emit linker patches.
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void EmitLinkerPatches(ArenaVector<LinkerPatch>* linker_patches) OVERRIDE;
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// Emit a write barrier.
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void MarkGCCard(Register temp,
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Register card,
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Register object,
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Register value,
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bool value_can_be_null);
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void GenerateMemoryBarrier(MemBarrierKind kind);
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Label* GetLabelOf(HBasicBlock* block) const {
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return CommonGetLabelOf<Label>(block_labels_, block);
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}
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void Initialize() OVERRIDE {
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block_labels_ = CommonInitializeLabels<Label>();
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}
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bool NeedsTwoRegisters(Primitive::Type type) const OVERRIDE {
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return type == Primitive::kPrimLong;
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}
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bool ShouldSplitLongMoves() const OVERRIDE { return true; }
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Label* GetFrameEntryLabel() { return &frame_entry_label_; }
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const X86InstructionSetFeatures& GetInstructionSetFeatures() const {
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return isa_features_;
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}
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void SetMethodAddressOffset(int32_t offset) {
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method_address_offset_ = offset;
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}
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int32_t GetMethodAddressOffset() const {
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return method_address_offset_;
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}
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int32_t ConstantAreaStart() const {
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return constant_area_start_;
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}
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Address LiteralDoubleAddress(double v, Register reg);
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Address LiteralFloatAddress(float v, Register reg);
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Address LiteralInt32Address(int32_t v, Register reg);
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Address LiteralInt64Address(int64_t v, Register reg);
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// Load a 32-bit value into a register in the most efficient manner.
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void Load32BitValue(Register dest, int32_t value);
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// Compare a register with a 32-bit value in the most efficient manner.
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void Compare32BitValue(Register dest, int32_t value);
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Address LiteralCaseTable(HX86PackedSwitch* switch_instr, Register reg, Register value);
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void Finalize(CodeAllocator* allocator) OVERRIDE;
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// Fast path implementation of ReadBarrier::Barrier for a heap
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// reference field load when Baker's read barriers are used.
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void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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Register obj,
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uint32_t offset,
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Location temp,
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bool needs_null_check);
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// Fast path implementation of ReadBarrier::Barrier for a heap
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// reference array load when Baker's read barriers are used.
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void GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction,
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Location ref,
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Register obj,
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uint32_t data_offset,
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Location index,
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Location temp,
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bool needs_null_check);
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// Generate a read barrier for a heap reference within `instruction`
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// using a slow path.
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//
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|
// A read barrier for an object reference read from the heap is
|
|
// implemented as a call to the artReadBarrierSlow runtime entry
|
|
// point, which is passed the values in locations `ref`, `obj`, and
|
|
// `offset`:
|
|
//
|
|
// mirror::Object* artReadBarrierSlow(mirror::Object* ref,
|
|
// mirror::Object* obj,
|
|
// uint32_t offset);
|
|
//
|
|
// The `out` location contains the value returned by
|
|
// artReadBarrierSlow.
|
|
//
|
|
// When `index` is provided (i.e. for array accesses), the offset
|
|
// value passed to artReadBarrierSlow is adjusted to take `index`
|
|
// into account.
|
|
void GenerateReadBarrierSlow(HInstruction* instruction,
|
|
Location out,
|
|
Location ref,
|
|
Location obj,
|
|
uint32_t offset,
|
|
Location index = Location::NoLocation());
|
|
|
|
// If read barriers are enabled, generate a read barrier for a heap
|
|
// reference using a slow path. If heap poisoning is enabled, also
|
|
// unpoison the reference in `out`.
|
|
void MaybeGenerateReadBarrierSlow(HInstruction* instruction,
|
|
Location out,
|
|
Location ref,
|
|
Location obj,
|
|
uint32_t offset,
|
|
Location index = Location::NoLocation());
|
|
|
|
// Generate a read barrier for a GC root within `instruction` using
|
|
// a slow path.
|
|
//
|
|
// A read barrier for an object reference GC root is implemented as
|
|
// a call to the artReadBarrierForRootSlow runtime entry point,
|
|
// which is passed the value in location `root`:
|
|
//
|
|
// mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root);
|
|
//
|
|
// The `out` location contains the value returned by
|
|
// artReadBarrierForRootSlow.
|
|
void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root);
|
|
|
|
// Ensure that prior stores complete to memory before subsequent loads.
|
|
// The locked add implementation will avoid serializing device memory, but will
|
|
// touch (but not change) the top of the stack.
|
|
// The 'non_temporal' parameter should be used to ensure ordering of non-temporal stores.
|
|
void MemoryFence(bool non_temporal = false) {
|
|
if (!non_temporal && isa_features_.PrefersLockedAddSynchronization()) {
|
|
assembler_.lock()->addl(Address(ESP, 0), Immediate(0));
|
|
} else {
|
|
assembler_.mfence();
|
|
}
|
|
}
|
|
|
|
void GenerateNop();
|
|
void GenerateImplicitNullCheck(HNullCheck* instruction);
|
|
void GenerateExplicitNullCheck(HNullCheck* instruction);
|
|
|
|
// When we don't know the proper offset for the value, we use kDummy32BitOffset.
|
|
// The correct value will be inserted when processing Assembler fixups.
|
|
static constexpr int32_t kDummy32BitOffset = 256;
|
|
|
|
private:
|
|
// Factored implementation of GenerateFieldLoadWithBakerReadBarrier
|
|
// and GenerateArrayLoadWithBakerReadBarrier.
|
|
void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction,
|
|
Location ref,
|
|
Register obj,
|
|
const Address& src,
|
|
Location temp,
|
|
bool needs_null_check);
|
|
|
|
Register GetInvokeStaticOrDirectExtraParameter(HInvokeStaticOrDirect* invoke, Register temp);
|
|
|
|
struct PcRelativeDexCacheAccessInfo {
|
|
PcRelativeDexCacheAccessInfo(const DexFile& dex_file, uint32_t element_off)
|
|
: target_dex_file(dex_file), element_offset(element_off), label() { }
|
|
|
|
const DexFile& target_dex_file;
|
|
uint32_t element_offset;
|
|
// NOTE: Label is bound to the end of the instruction that has an embedded 32-bit offset.
|
|
Label label;
|
|
};
|
|
|
|
// Labels for each block that will be compiled.
|
|
Label* block_labels_; // Indexed by block id.
|
|
Label frame_entry_label_;
|
|
LocationsBuilderX86 location_builder_;
|
|
InstructionCodeGeneratorX86 instruction_visitor_;
|
|
ParallelMoveResolverX86 move_resolver_;
|
|
X86Assembler assembler_;
|
|
const X86InstructionSetFeatures& isa_features_;
|
|
|
|
// Method patch info. Using ArenaDeque<> which retains element addresses on push/emplace_back().
|
|
ArenaDeque<MethodPatchInfo<Label>> method_patches_;
|
|
ArenaDeque<MethodPatchInfo<Label>> relative_call_patches_;
|
|
// PC-relative DexCache access info.
|
|
ArenaDeque<PcRelativeDexCacheAccessInfo> pc_relative_dex_cache_patches_;
|
|
// Patch locations for patchoat where the linker doesn't do any other work.
|
|
ArenaDeque<Label> simple_patches_;
|
|
// String patch locations.
|
|
ArenaDeque<StringPatchInfo<Label>> string_patches_;
|
|
|
|
// Offset to the start of the constant area in the assembled code.
|
|
// Used for fixups to the constant area.
|
|
int32_t constant_area_start_;
|
|
|
|
// Fixups for jump tables that need to be patched after the constant table is generated.
|
|
ArenaVector<JumpTableRIPFixup*> fixups_to_jump_tables_;
|
|
|
|
// If there is a HX86ComputeBaseMethodAddress instruction in the graph
|
|
// (which shall be the sole instruction of this kind), subtracting this offset
|
|
// from the value contained in the out register of this HX86ComputeBaseMethodAddress
|
|
// instruction gives the address of the start of this method.
|
|
int32_t method_address_offset_;
|
|
|
|
DISALLOW_COPY_AND_ASSIGN(CodeGeneratorX86);
|
|
};
|
|
|
|
} // namespace x86
|
|
} // namespace art
|
|
|
|
#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_H_
|