249 lines
6.4 KiB
C
249 lines
6.4 KiB
C
/*
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*Copyright (C) 2015 The Android Open Source Project
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*
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*Licensed under the Apache License, Version 2.0 (the "License");
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*you may not use this file except in compliance with the License.
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*You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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*Unless required by applicable law or agreed to in writing, software
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*distributed under the License is distributed on an "AS IS" BASIS,
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*WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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*See the License for the specific language governing permissions and
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*limitations under the License.
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*
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* This file was copied from https://github.com/devttys0/libmpsse.git (sha1
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* f1a6744b), and modified to suite the Chromium OS project.
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*/
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#ifndef TRUNKS_FTDI_MPSSE_H_
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#define TRUNKS_FTDI_MPSSE_H_
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#include <libftdi1/ftdi.h>
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#include <stdint.h>
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#define MPSSE_OK 0
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#define MPSSE_FAIL -1
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#define MSB 0x00
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#define LSB 0x08
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#define CHUNK_SIZE 65535
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#define SPI_RW_SIZE (63 * 1024)
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#define SPI_TRANSFER_SIZE 512
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#define I2C_TRANSFER_SIZE 64
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#define LATENCY_MS 2
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#define TIMEOUT_DIVISOR 1000000
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#define USB_TIMEOUT 120000
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#define SETUP_DELAY 25000
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#define BITMODE_RESET 0
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#define BITMODE_MPSSE 2
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#define CMD_SIZE 3
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#define MAX_SETUP_COMMANDS 10
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#define SS_TX_COUNT 3
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#define LOW 0
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#define HIGH 1
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#define NUM_GPIOL_PINS 4
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#define NUM_GPIO_PINS 12
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#define NULL_CONTEXT_ERROR_MSG "NULL MPSSE context pointer!"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* FTDI interfaces */
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enum interface {
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IFACE_ANY = INTERFACE_ANY,
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IFACE_A = INTERFACE_A,
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IFACE_B = INTERFACE_B,
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IFACE_C = INTERFACE_C,
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IFACE_D = INTERFACE_D
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};
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/* Common clock rates */
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enum clock_rates {
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ONE_HUNDRED_KHZ = 100000,
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FOUR_HUNDRED_KHZ = 400000,
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ONE_MHZ = 1000000,
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TWO_MHZ = 2000000,
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FIVE_MHZ = 5000000,
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SIX_MHZ = 6000000,
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TEN_MHZ = 10000000,
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TWELVE_MHZ = 12000000,
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FIFTEEN_MHZ = 15000000,
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THIRTY_MHZ = 30000000,
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SIXTY_MHZ = 60000000
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};
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/* Supported MPSSE modes */
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enum modes {
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SPI0 = 1,
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SPI1 = 2,
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SPI2 = 3,
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SPI3 = 4,
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I2C = 5,
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GPIO = 6,
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BITBANG = 7,
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};
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enum pins {
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SK = 1,
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DO = 2,
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DI = 4,
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CS = 8,
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GPIO0 = 16,
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GPIO1 = 32,
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GPIO2 = 64,
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GPIO3 = 128
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};
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enum gpio_pins {
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GPIOL0 = 0,
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GPIOL1 = 1,
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GPIOL2 = 2,
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GPIOL3 = 3,
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GPIOH0 = 4,
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GPIOH1 = 5,
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GPIOH2 = 6,
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GPIOH3 = 7,
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GPIOH4 = 8,
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GPIOH5 = 9,
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GPIOH6 = 10,
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GPIOH7 = 11
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};
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enum i2c_ack { ACK = 0, NACK = 1 };
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/* SK/DO/CS and GPIOs are outputs, DI is an input */
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#define DEFAULT_TRIS (SK | DO | CS | GPIO0 | GPIO1 | GPIO2 | GPIO3)
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#define DEFAULT_PORT (SK | CS) /* SK and CS are high, all others low */
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enum mpsse_commands {
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INVALID_COMMAND = 0xAB,
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ENABLE_ADAPTIVE_CLOCK = 0x96,
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DISABLE_ADAPTIVE_CLOCK = 0x97,
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ENABLE_3_PHASE_CLOCK = 0x8C,
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DISABLE_3_PHASE_CLOCK = 0x8D,
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TCK_X5 = 0x8A,
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TCK_D5 = 0x8B,
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CLOCK_N_CYCLES = 0x8E,
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CLOCK_N8_CYCLES = 0x8F,
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PULSE_CLOCK_IO_HIGH = 0x94,
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PULSE_CLOCK_IO_LOW = 0x95,
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CLOCK_N8_CYCLES_IO_HIGH = 0x9C,
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CLOCK_N8_CYCLES_IO_LOW = 0x9D,
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TRISTATE_IO = 0x9E,
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};
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enum low_bits_status { STARTED, STOPPED };
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struct vid_pid {
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int vid;
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int pid;
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char* description;
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};
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struct mpsse_context {
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char* description;
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struct ftdi_context ftdi;
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enum modes mode;
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enum low_bits_status status;
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int flush_after_read;
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int vid;
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int pid;
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int clock;
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int xsize;
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uint8_t endianess;
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uint8_t opened;
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uint8_t tris;
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uint8_t pstart;
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uint8_t pstop;
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uint8_t pidle;
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uint8_t gpioh;
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uint8_t trish;
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uint8_t bitbang;
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uint8_t tx;
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uint8_t rx;
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uint8_t txrx;
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uint8_t tack;
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uint8_t rack;
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};
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struct mpsse_context* MPSSE(enum modes mode, int freq, int endianess);
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struct mpsse_context* Open(int vid,
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int pid,
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enum modes mode,
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int freq,
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int endianess,
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int interface,
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const char* description,
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const char* serial);
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struct mpsse_context* OpenIndex(int vid,
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int pid,
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enum modes mode,
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int freq,
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int endianess,
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int interface,
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const char* description,
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const char* serial,
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int index);
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void Close(struct mpsse_context* mpsse);
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const char* ErrorString(struct mpsse_context* mpsse);
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int SetMode(struct mpsse_context* mpsse, int endianess);
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void EnableBitmode(struct mpsse_context* mpsse, int tf);
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int SetClock(struct mpsse_context* mpsse, uint32_t freq);
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int GetClock(struct mpsse_context* mpsse);
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int GetVid(struct mpsse_context* mpsse);
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int GetPid(struct mpsse_context* mpsse);
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const char* GetDescription(struct mpsse_context* mpsse);
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int SetLoopback(struct mpsse_context* mpsse, int enable);
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void SetCSIdle(struct mpsse_context* mpsse, int idle);
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int Start(struct mpsse_context* mpsse);
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int Write(struct mpsse_context* mpsse, const void* data, int size);
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int Stop(struct mpsse_context* mpsse);
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int GetAck(struct mpsse_context* mpsse);
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void SetAck(struct mpsse_context* mpsse, int ack);
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void SendAcks(struct mpsse_context* mpsse);
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void SendNacks(struct mpsse_context* mpsse);
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void FlushAfterRead(struct mpsse_context* mpsse, int tf);
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int PinHigh(struct mpsse_context* mpsse, int pin);
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int PinLow(struct mpsse_context* mpsse, int pin);
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int SetDirection(struct mpsse_context* mpsse, uint8_t direction);
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int WriteBits(struct mpsse_context* mpsse, char bits, size_t size);
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char ReadBits(struct mpsse_context* mpsse, int size);
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int WritePins(struct mpsse_context* mpsse, uint8_t data);
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int ReadPins(struct mpsse_context* mpsse);
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int PinState(struct mpsse_context* mpsse, int pin, int state);
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int Tristate(struct mpsse_context* mpsse);
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char Version(void);
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#ifdef SWIGPYTHON
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typedef struct swig_string_data {
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int size;
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char* data;
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} swig_string_data;
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swig_string_data Read(struct mpsse_context* mpsse, int size);
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swig_string_data Transfer(struct mpsse_context* mpsse, char* data, int size);
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#else
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uint8_t* Read(struct mpsse_context* mpsse, int size);
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uint8_t* Transfer(struct mpsse_context* mpsse,
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uint8_t* data, int size);
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int FastWrite(struct mpsse_context* mpsse, char* data, int size);
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int FastRead(struct mpsse_context* mpsse, char* data, int size);
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int FastTransfer(struct mpsse_context* mpsse,
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char* wdata,
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char* rdata,
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int size);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* TRUNKS_FTDI_MPSSE_H_ */
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