605 lines
20 KiB
C
605 lines
20 KiB
C
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#include <stdio.h>
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#include <stdlib.h>
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#define HAVE_SSE2 1
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/* DO NOT COMPILE WITH -O/-O2/-O3 ! GENERATES INVALID ASSEMBLY. */
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/* mmx.h
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MultiMedia eXtensions GCC interface library for IA32.
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To use this library, simply include this header file
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and compile with GCC. You MUST have inlining enabled
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in order for mmx_ok() to work; this can be done by
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simply using -O on the GCC command line.
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Compiling with -DMMX_TRACE will cause detailed trace
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output to be sent to stderr for each mmx operation.
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This adds lots of code, and obviously slows execution to
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a crawl, but can be very useful for debugging.
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THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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AND FITNESS FOR ANY PARTICULAR PURPOSE.
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June 11, 1998 by H. Dietz and R. Fisher
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*/
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/* The type of an value that fits in an MMX register
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(note that long long constant values MUST be suffixed
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by LL and unsigned long long values by ULL, lest
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they be truncated by the compiler)
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*/
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typedef union {
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long long q; /* Quadword (64-bit) value */
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unsigned long long uq; /* Unsigned Quadword */
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int d[2]; /* 2 Doubleword (32-bit) values */
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unsigned int ud[2]; /* 2 Unsigned Doubleword */
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short w[4]; /* 4 Word (16-bit) values */
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unsigned short uw[4]; /* 4 Unsigned Word */
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char b[8]; /* 8 Byte (8-bit) values */
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unsigned char ub[8]; /* 8 Unsigned Byte */
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} mmx_t;
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/* Function to test if mmx instructions are supported...
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*/
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inline extern int
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mmx_ok(void)
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{
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/* Returns 1 if mmx instructions are ok,
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0 if hardware does not support mmx
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*/
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register int ok = 0;
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__asm__ __volatile__ (
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/* Get CPU version information */
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"movl $1, %%eax\n\t"
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"cpuid\n\t"
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"movl %%edx, %0"
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: "=a" (ok)
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: /* no input */
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);
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return((ok & 0x800000) == 0x800000);
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}
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/* Helper functions for the instruction macros that follow...
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(note that memory-to-register, m2r, instructions are nearly
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as efficient as register-to-register, r2r, instructions;
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however, memory-to-memory instructions are really simulated
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as a convenience, and are only 1/3 as efficient)
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*/
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#ifdef MMX_TRACE
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/* Include the stuff for printing a trace to stderr...
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*/
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#include <stdio.h>
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#define mmx_m2r(op, mem, reg) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mem); \
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fprintf(stderr, #op "_m2r(" #mem "=0x%016llx, ", mmx_trace.q); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (mem)); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
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}
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#define mmx_r2m(op, reg, mem) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2m(" #reg "=0x%016llx, ", mmx_trace.q); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=X" (mem) \
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: /* nothing */ ); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%016llx\n", mmx_trace.q); \
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}
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#define mmx_r2r(op, regs, regd) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #regs ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2r(" #regs "=0x%016llx, ", mmx_trace.q); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%016llx\n", mmx_trace.q); \
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}
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#define mmx_m2m(op, mems, memd) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mems); \
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fprintf(stderr, #op "_m2m(" #mems "=0x%016llx, ", mmx_trace.q); \
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mmx_trace = (memd); \
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fprintf(stderr, #memd "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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#op " %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (memd) \
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: "X" (mems)); \
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mmx_trace = (memd); \
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fprintf(stderr, #memd "=0x%016llx\n", mmx_trace.q); \
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}
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#else
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/* These macros are a lot simpler without the tracing...
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*/
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#define mmx_m2r(op, mem, reg) \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (mem))
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#define mmx_r2m(op, reg, mem) \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=X" (mem) \
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: /* nothing */ )
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#define mmx_r2r(op, regs, regd) \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd)
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#define mmx_m2m(op, mems, memd) \
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__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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#op " %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (memd) \
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: "X" (mems))
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#endif
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/* 1x64 MOVe Quadword
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(this is both a load and a store...
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in fact, it is the only way to store)
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*/
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#define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
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#define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
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#define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
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#define movq(vars, vard) \
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__asm__ __volatile__ ("movq %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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/* 1x64 MOVe Doubleword
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(like movq, this is both load and store...
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but is most useful for moving things between
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mmx registers and ordinary registers)
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*/
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#define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
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#define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
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#define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
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#define movd(vars, vard) \
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__asm__ __volatile__ ("movd %1, %%mm0\n\t" \
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"movd %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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/* 2x32, 4x16, and 8x8 Parallel ADDs
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*/
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#define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
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#define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
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#define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
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#define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
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#define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
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#define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
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#define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
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#define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
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#define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
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/* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
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*/
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#define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
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#define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
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#define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
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#define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
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#define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
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#define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
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/* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
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*/
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#define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
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#define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
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#define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
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#define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
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#define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
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#define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
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/* 2x32, 4x16, and 8x8 Parallel SUBs
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*/
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#define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
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#define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
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#define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
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#define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
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#define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
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#define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
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#define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
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#define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
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#define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
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/* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
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*/
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#define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
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#define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
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#define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
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#define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
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#define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
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#define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
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/* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
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*/
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#define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
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#define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
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#define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
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#define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
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#define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
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#define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
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/* 4x16 Parallel MULs giving Low 4x16 portions of results
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*/
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#define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
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#define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
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#define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
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/* 4x16 Parallel MULs giving High 4x16 portions of results
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*/
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#define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
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#define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
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#define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
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/* 4x16->2x32 Parallel Mul-ADD
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(muls like pmullw, then adds adjacent 16-bit fields
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in the multiply result to make the final 2x32 result)
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*/
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#define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
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#define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
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#define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
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/* 1x64 bitwise AND
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*/
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#define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
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#define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
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#define pand(vars, vard) mmx_m2m(pand, vars, vard)
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/* 1x64 bitwise AND with Not the destination
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*/
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#define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
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#define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
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#define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
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/* 1x64 bitwise OR
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*/
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#define por_m2r(var, reg) mmx_m2r(por, var, reg)
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#define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
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#define por(vars, vard) mmx_m2m(por, vars, vard)
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/* 1x64 bitwise eXclusive OR
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*/
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#define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
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#define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
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#define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
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/* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
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(resulting fields are either 0 or -1)
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*/
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#define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
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#define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
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#define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
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#define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
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#define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
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#define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
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#define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
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#define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
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#define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
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/* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
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(resulting fields are either 0 or -1)
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*/
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#define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
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#define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
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#define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
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#define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
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#define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
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#define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
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#define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
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#define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
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#define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
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/* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
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*/
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#define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
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#define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
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#define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
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#define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
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#define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
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#define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
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#define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
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#define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
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#define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
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/* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
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*/
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#define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
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#define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
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#define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
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#define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
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#define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
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#define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
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#define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
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#define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
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#define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
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/* 2x32 and 4x16 Parallel Shift Right Arithmetic
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*/
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#define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
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#define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
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#define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
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#define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
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#define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
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#define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
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/* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
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(packs source and dest fields into dest in that order)
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*/
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#define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
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#define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
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#define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
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#define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
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#define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
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#define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
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/* 4x16->8x8 PACK and Unsigned Saturate
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(packs source and dest fields into dest in that order)
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*/
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#define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
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#define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
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#define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
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/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
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(interleaves low half of dest with low half of source
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as padding in each result field)
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*/
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#define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
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#define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
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#define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
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#define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
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#define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
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#define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
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#define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
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#define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
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#define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
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/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
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(interleaves high half of dest with high half of source
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as padding in each result field)
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*/
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#define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
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#define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
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#define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
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#define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
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#define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
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#define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
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#define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
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#define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
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#define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
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/* 1x64 add/sub -- this is in sse2, not in mmx. */
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#define paddq_m2r(var, reg) mmx_m2r(paddq, var, reg)
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#define paddq_r2r(regs, regd) mmx_r2r(paddq, regs, regd)
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#define paddq(vars, vard) mmx_m2m(paddq, vars, vard)
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#define psubq_m2r(var, reg) mmx_m2r(psubq, var, reg)
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#define psubq_r2r(regs, regd) mmx_r2r(psubq, regs, regd)
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#define psubq(vars, vard) mmx_m2m(psubq, vars, vard)
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/* Empty MMx State
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(used to clean-up when going from mmx to float use
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of the registers that are shared by both; note that
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there is no float-to-mmx operation needed, because
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only the float tag word info is corruptible)
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*/
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#ifdef MMX_TRACE
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#define emms() \
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{ \
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fprintf(stderr, "emms()\n"); \
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__asm__ __volatile__ ("emms"); \
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}
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#else
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#define emms() __asm__ __volatile__ ("emms")
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#endif
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void mkRand( mmx_t* mm )
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{
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mm->uw[0] = 0xFFFF & (random() >> 7);
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mm->uw[1] = 0xFFFF & (random() >> 7);
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mm->uw[2] = 0xFFFF & (random() >> 7);
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mm->uw[3] = 0xFFFF & (random() >> 7);
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}
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int main( void )
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{
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int i;
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// int rval;
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mmx_t ma;
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mmx_t mb;
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mmx_t ma0, mb0;
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movq_r2r(mm0, mm1);
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// rval = mmx_ok();
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/* Announce return value of mmx_ok() */
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// printf("Value returned from init was %x.", rval);
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// printf(" (Indicates MMX %s available)\n\n",(rval)? "is" : "not");
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// fflush(stdout); fflush(stdout);
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// if(rval)
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#define do_test(_name, _operation) \
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for (i = 0; i < 25000; i++) { \
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mkRand(&ma); \
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mkRand(&mb); \
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ma0 = ma; mb0 = mb; \
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_operation; \
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fprintf(stdout, "%s ( %016llx, %016llx ) -> %016llx\n", \
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_name, ma0.q, mb0.q, mb.q); \
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fflush(stdout); \
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}
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{
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do_test("paddd", paddd(ma,mb));
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do_test("paddw", paddw(ma,mb));
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do_test("paddb", paddb(ma,mb));
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do_test("paddsw", paddsw(ma,mb));
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do_test("paddsb", paddsb(ma,mb));
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do_test("paddusw", paddusw(ma,mb));
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do_test("paddusb", paddusb(ma,mb));
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do_test("psubd", psubd(ma,mb));
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do_test("psubw", psubw(ma,mb));
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do_test("psubb", psubb(ma,mb));
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do_test("psubsw", psubsw(ma,mb));
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do_test("psubsb", psubsb(ma,mb));
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do_test("psubusw", psubusw(ma,mb));
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|
do_test("psubusb", psubusb(ma,mb));
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|
|
do_test("pmulhw", pmulhw(ma,mb));
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do_test("pmullw", pmullw(ma,mb));
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|
|
|
do_test("pmaddwd", pmaddwd(ma,mb));
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|
|
|
do_test("pcmpeqd", pcmpeqd(ma,mb));
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|
do_test("pcmpeqw", pcmpeqw(ma,mb));
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|
do_test("pcmpeqb", pcmpeqb(ma,mb));
|
|
|
|
do_test("pcmpgtd", pcmpgtd(ma,mb));
|
|
do_test("pcmpgtw", pcmpgtw(ma,mb));
|
|
do_test("pcmpgtb", pcmpgtb(ma,mb));
|
|
|
|
do_test("packssdw", packssdw(ma,mb));
|
|
do_test("packsswb", packsswb(ma,mb));
|
|
do_test("packuswb", packuswb(ma,mb));
|
|
|
|
do_test("punpckhdq", punpckhdq(ma,mb));
|
|
do_test("punpckhwd", punpckhwd(ma,mb));
|
|
do_test("punpckhbw", punpckhbw(ma,mb));
|
|
|
|
do_test("punpckldq", punpckldq(ma,mb));
|
|
do_test("punpcklwd", punpcklwd(ma,mb));
|
|
do_test("punpcklbw", punpcklbw(ma,mb));
|
|
|
|
do_test("pand", pand(ma,mb));
|
|
do_test("pandn", pandn(ma,mb));
|
|
do_test("por", por(ma,mb));
|
|
do_test("pxor", pxor(ma,mb));
|
|
|
|
do_test("psllq", psllq(ma,mb));
|
|
do_test("pslld", pslld(ma,mb));
|
|
do_test("psllw", psllw(ma,mb));
|
|
|
|
do_test("psrlq", psrlq(ma,mb));
|
|
do_test("psrld", psrld(ma,mb));
|
|
do_test("psrlw", psrlw(ma,mb));
|
|
|
|
do_test("psrad", psrad(ma,mb));
|
|
do_test("psraw", psraw(ma,mb));
|
|
|
|
#if HAVE_SSE2
|
|
do_test("paddq", paddq(ma,mb));
|
|
do_test("psubq", psubq(ma,mb));
|
|
#endif
|
|
|
|
emms();
|
|
}
|
|
|
|
/* Clean-up and exit nicely */
|
|
exit(0);
|
|
}
|