133 lines
2.4 KiB
C
133 lines
2.4 KiB
C
#ifndef ARCH_PPC_H
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#define ARCH_PPC_H
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#include <unistd.h>
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#include <stdlib.h>
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#include <sys/types.h>
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#include <sys/wait.h>
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#define FIO_ARCH (arch_ppc)
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#ifndef __NR_ioprio_set
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#define __NR_ioprio_set 273
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#define __NR_ioprio_get 274
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#endif
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#ifndef __NR_fadvise64
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#define __NR_fadvise64 233
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#endif
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#ifndef __NR_sys_splice
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#define __NR_sys_splice 283
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#define __NR_sys_tee 284
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#define __NR_sys_vmsplice 285
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#endif
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#define nop do { } while (0)
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#ifdef __powerpc64__
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#define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
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#else
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#define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
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#endif
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#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
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static inline int __ilog2(unsigned long bitmask)
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{
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int lz;
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asm ("cntlzw %0,%1" : "=r" (lz) : "r" (bitmask));
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return 31 - lz;
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}
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static inline int arch_ffz(unsigned long bitmask)
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{
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if ((bitmask = ~bitmask) == 0)
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return 32;
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return __ilog2(bitmask & -bitmask);
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}
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static inline unsigned int mfspr(unsigned int reg)
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{
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unsigned int val;
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asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
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return val;
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}
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#define SPRN_TBRL 0x10C /* Time Base Register Lower */
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#define SPRN_TBRU 0x10D /* Time Base Register Upper */
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#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
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#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
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static inline unsigned long long get_cpu_clock(void)
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{
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unsigned int tbl, tbu0, tbu1;
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unsigned long long ret;
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do {
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if (arch_flags & ARCH_FLAG_1) {
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tbu0 = mfspr(SPRN_ATBU);
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tbl = mfspr(SPRN_ATBL);
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tbu1 = mfspr(SPRN_ATBU);
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} else {
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tbu0 = mfspr(SPRN_TBRU);
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tbl = mfspr(SPRN_TBRL);
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tbu1 = mfspr(SPRN_TBRU);
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}
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} while (tbu0 != tbu1);
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ret = (((unsigned long long)tbu0) << 32) | tbl;
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return ret;
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}
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#if 0
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static void atb_child(void)
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{
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arch_flags |= ARCH_FLAG_1;
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get_cpu_clock();
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_exit(0);
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}
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static void atb_clocktest(void)
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{
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pid_t pid;
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pid = fork();
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if (!pid)
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atb_child();
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else if (pid != -1) {
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int status;
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pid = wait(&status);
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if (pid == -1 || !WIFEXITED(status))
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arch_flags &= ~ARCH_FLAG_1;
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else
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arch_flags |= ARCH_FLAG_1;
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}
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}
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#endif
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#define ARCH_HAVE_INIT
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extern int tsc_reliable;
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static inline int arch_init(char *envp[])
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{
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#if 0
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tsc_reliable = 1;
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atb_clocktest();
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#endif
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return 0;
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}
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#define ARCH_HAVE_FFZ
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/*
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* We don't have it on all platforms, lets comment this out until we
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* can handle it more intelligently.
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*
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* #define ARCH_HAVE_CPU_CLOCK
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*/
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#endif
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