136 lines
5.5 KiB
C
136 lines
5.5 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef VIRTGPU_DRM_H
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#define VIRTGPU_DRM_H
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#include <stddef.h>
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#include "drm/drm.h"
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_VIRTGPU_MAP 0x01
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#define DRM_VIRTGPU_EXECBUFFER 0x02
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#define DRM_VIRTGPU_GETPARAM 0x03
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#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_VIRTGPU_RESOURCE_INFO 0x05
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#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
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#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
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#define DRM_VIRTGPU_WAIT 0x08
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_VIRTGPU_GET_CAPS 0x09
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struct drm_virtgpu_map {
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uint64_t offset;
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uint32_t handle;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t pad;
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};
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struct drm_virtgpu_execbuffer {
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uint32_t flags;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t size;
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uint64_t command;
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uint64_t bo_handles;
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uint32_t num_bo_handles;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t pad;
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};
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#define VIRTGPU_PARAM_3D_FEATURES 1
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struct drm_virtgpu_getparam {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint64_t param;
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uint64_t value;
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};
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struct drm_virtgpu_resource_create {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t target;
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uint32_t format;
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uint32_t bind;
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uint32_t width;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t height;
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uint32_t depth;
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uint32_t array_size;
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uint32_t last_level;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t nr_samples;
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uint32_t flags;
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uint32_t bo_handle;
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uint32_t res_handle;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t size;
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uint32_t stride;
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};
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struct drm_virtgpu_resource_info {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t bo_handle;
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uint32_t res_handle;
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uint32_t size;
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uint32_t stride;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct drm_virtgpu_3d_box {
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uint32_t x;
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uint32_t y;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t z;
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uint32_t w;
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uint32_t h;
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uint32_t d;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct drm_virtgpu_3d_transfer_to_host {
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uint32_t bo_handle;
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struct drm_virtgpu_3d_box box;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t level;
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uint32_t offset;
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};
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struct drm_virtgpu_3d_transfer_from_host {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t bo_handle;
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struct drm_virtgpu_3d_box box;
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uint32_t level;
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uint32_t offset;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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#define VIRTGPU_WAIT_NOWAIT 1
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struct drm_virtgpu_3d_wait {
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uint32_t handle;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t flags;
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};
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struct drm_virtgpu_get_caps {
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uint32_t cap_set_id;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t cap_set_ver;
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uint64_t addr;
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uint32_t size;
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uint32_t pad;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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#define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
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#define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
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#define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)
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#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)
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#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)
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#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
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#define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
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#endif
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