29 lines
1.3 KiB
ArmAsm
29 lines
1.3 KiB
ArmAsm
%default {"preinstr":"", "result":"a0", "chkzero":"0"}
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/*
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* Generic 32-bit "/2addr" binary operation. Provide an "instr" line
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* that specifies an instruction that performs "result = a0 op a1".
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* This could be an MIPS instruction or a function call.
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*
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* If "chkzero" is set to 1, we perform a divide-by-zero check on
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* vCC (a1). Useful for integer division and modulus.
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*
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* For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
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* rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
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* shl-int/2addr, shr-int/2addr, ushr-int/2addr
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*/
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/* binop/2addr vA, vB */
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GET_OPA4(rOBJ) # rOBJ <- A+
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GET_OPB(a3) # a3 <- B
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GET_VREG(a0, rOBJ) # a0 <- vA
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GET_VREG(a1, a3) # a1 <- vB
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.if $chkzero
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# is second operand zero?
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beqz a1, common_errDivideByZero
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.endif
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FETCH_ADVANCE_INST(1) # advance rPC, load rINST
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$preinstr # optional op
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$instr # $result <- op, a0-a3 changed
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GET_INST_OPCODE(t0) # extract opcode from rINST
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SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result
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/* 10-13 instructions */
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