35 lines
1.7 KiB
ArmAsm
35 lines
1.7 KiB
ArmAsm
%default {"extract":"asr r1, r3, #8", "result":"r0", "chkzero":"0"}
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/*
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* Generic 32-bit "lit8" binary operation. Provide an "instr" line
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* that specifies an instruction that performs "result = r0 op r1".
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* This could be an ARM instruction or a function call. (If the result
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* comes back in a register other than r0, you can override "result".)
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*
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* You can override "extract" if the extraction of the literal value
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* from r3 to r1 is not the default "asr r1, r3, #8". The extraction
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* can be omitted completely if the shift is embedded in "instr".
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*
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* If "chkzero" is set to 1, we perform a divide-by-zero check on
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* vCC (r1). Useful for integer division and modulus.
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*
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* For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
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* rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
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* shl-int/lit8, shr-int/lit8, ushr-int/lit8
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*/
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/* binop/lit8 vAA, vBB, #+CC */
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FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC)
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mov r9, rINST, lsr #8 @ r9<- AA
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and r2, r3, #255 @ r2<- BB
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GET_VREG r0, r2 @ r0<- vBB
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$extract @ optional; typically r1<- ssssssCC (sign extended)
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.if $chkzero
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@cmp r1, #0 @ is second operand zero?
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beq common_errDivideByZero
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.endif
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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$instr @ $result<- op, r0-r3 changed
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG $result, r9 @ vAA<- $result
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GOTO_OPCODE ip @ jump to next instruction
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/* 10-12 instructions */
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