35 lines
1.7 KiB
ArmAsm
35 lines
1.7 KiB
ArmAsm
%default {"preinstr":"", "result":"r0", "chkzero":"0"}
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/*
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* Generic 32-bit binary operation. Provide an "instr" line that
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* specifies an instruction that performs "result = r0 op r1".
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* This could be an ARM instruction or a function call. (If the result
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* comes back in a register other than r0, you can override "result".)
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*
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* If "chkzero" is set to 1, we perform a divide-by-zero check on
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* vCC (r1). Useful for integer division and modulus. Note that we
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* *don't* check for (INT_MIN / -1) here, because the ARM math lib
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* handles it correctly.
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*
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* For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
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* xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
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* mul-float, div-float, rem-float
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*/
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/* binop vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov r9, rINST, lsr #8 @ r9<- AA
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mov r3, r0, lsr #8 @ r3<- CC
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and r2, r0, #255 @ r2<- BB
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GET_VREG r1, r3 @ r1<- vCC
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GET_VREG r0, r2 @ r0<- vBB
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.if $chkzero
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cmp r1, #0 @ is second operand zero?
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beq common_errDivideByZero
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.endif
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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$preinstr @ optional op; may set condition codes
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$instr @ $result<- op, r0-r3 changed
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG $result, r9 @ vAA<- $result
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GOTO_OPCODE ip @ jump to next instruction
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/* 11-14 instructions */
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