209 lines
5 KiB
C
209 lines
5 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef MLX5_ABI_USER_H
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#define MLX5_ABI_USER_H
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#include <linux/types.h>
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enum {
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MLX5_QP_FLAG_SIGNATURE = 1 << 0,
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MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
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};
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enum {
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MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
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};
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enum {
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MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
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};
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#define MLX5_IB_UVERBS_ABI_VERSION 1
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struct mlx5_ib_alloc_ucontext_req {
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__u32 total_num_uuars;
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__u32 num_low_latency_uuars;
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};
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struct mlx5_ib_alloc_ucontext_req_v2 {
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__u32 total_num_uuars;
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__u32 num_low_latency_uuars;
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__u32 flags;
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__u32 comp_mask;
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__u8 max_cqe_version;
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__u8 reserved0;
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__u16 reserved1;
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__u32 reserved2;
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};
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enum mlx5_ib_alloc_ucontext_resp_mask {
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
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};
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enum mlx5_user_cmds_supp_uhw {
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MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
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MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
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};
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struct mlx5_ib_alloc_ucontext_resp {
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__u32 qp_tab_size;
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__u32 bf_reg_size;
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__u32 tot_uuars;
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__u32 cache_line_size;
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__u16 max_sq_desc_sz;
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__u16 max_rq_desc_sz;
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__u32 max_send_wqebb;
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__u32 max_recv_wr;
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__u32 max_srq_recv_wr;
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__u16 num_ports;
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__u16 reserved1;
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__u32 comp_mask;
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__u32 response_length;
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__u8 cqe_version;
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__u8 cmds_supp_uhw;
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__u16 reserved2;
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__u64 hca_core_clock_offset;
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};
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struct mlx5_ib_alloc_pd_resp {
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__u32 pdn;
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};
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struct mlx5_ib_tso_caps {
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__u32 max_tso;
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__u32 supported_qpts;
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};
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struct mlx5_ib_rss_caps {
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__u64 rx_hash_fields_mask;
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__u8 rx_hash_function;
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__u8 reserved[7];
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};
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enum mlx5_ib_cqe_comp_res_format {
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MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
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MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
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MLX5_IB_CQE_RES_RESERVED = 1 << 2,
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};
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struct mlx5_ib_cqe_comp_caps {
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__u32 max_num;
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__u32 supported_format;
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};
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struct mlx5_packet_pacing_caps {
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__u32 qp_rate_limit_min;
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__u32 qp_rate_limit_max;
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__u32 supported_qpts;
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__u32 reserved;
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};
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struct mlx5_ib_query_device_resp {
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__u32 comp_mask;
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__u32 response_length;
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struct mlx5_ib_tso_caps tso_caps;
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struct mlx5_ib_rss_caps rss_caps;
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struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
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struct mlx5_packet_pacing_caps packet_pacing_caps;
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__u32 mlx5_ib_support_multi_pkt_send_wqes;
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__u32 reserved;
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};
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struct mlx5_ib_create_cq {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 cqe_size;
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__u8 cqe_comp_en;
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__u8 cqe_comp_res_format;
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__u16 reserved;
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};
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struct mlx5_ib_create_cq_resp {
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__u32 cqn;
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__u32 reserved;
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};
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struct mlx5_ib_resize_cq {
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__u64 buf_addr;
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__u16 cqe_size;
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__u16 reserved0;
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__u32 reserved1;
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};
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struct mlx5_ib_create_srq {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 flags;
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__u32 reserved0;
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__u32 uidx;
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__u32 reserved1;
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};
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struct mlx5_ib_create_srq_resp {
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__u32 srqn;
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__u32 reserved;
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};
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struct mlx5_ib_create_qp {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 sq_wqe_count;
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__u32 rq_wqe_count;
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__u32 rq_wqe_shift;
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__u32 flags;
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__u32 uidx;
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__u32 reserved0;
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__u64 sq_buf_addr;
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};
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enum mlx5_rx_hash_function_flags {
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MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
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};
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enum mlx5_rx_hash_fields {
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MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
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MLX5_RX_HASH_DST_IPV4 = 1 << 1,
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MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
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MLX5_RX_HASH_DST_IPV6 = 1 << 3,
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MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
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MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
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MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
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MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
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};
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struct mlx5_ib_create_qp_rss {
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__u64 rx_hash_fields_mask;
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__u8 rx_hash_function;
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__u8 rx_key_len;
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__u8 reserved[6];
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__u8 rx_hash_key[128];
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__u32 comp_mask;
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__u32 reserved1;
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};
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struct mlx5_ib_create_qp_resp {
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__u32 uuar_index;
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};
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struct mlx5_ib_alloc_mw {
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__u32 comp_mask;
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__u8 num_klms;
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__u8 reserved1;
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__u16 reserved2;
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};
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struct mlx5_ib_create_wq {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 rq_wqe_count;
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__u32 rq_wqe_shift;
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__u32 user_index;
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__u32 flags;
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__u32 comp_mask;
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__u32 reserved;
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};
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struct mlx5_ib_create_ah_resp {
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__u32 response_length;
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__u8 dmac[ETH_ALEN];
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__u8 reserved[6];
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};
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struct mlx5_ib_create_wq_resp {
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__u32 response_length;
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__u32 reserved;
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};
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struct mlx5_ib_create_rwq_ind_tbl_resp {
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__u32 response_length;
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__u32 reserved;
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};
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struct mlx5_ib_modify_wq {
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__u32 comp_mask;
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__u32 reserved;
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};
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#endif
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