156 lines
6.6 KiB
C++
156 lines
6.6 KiB
C++
/*
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* Copyright (C) 2017 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_SCHEDULER_ARM_H_
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#define ART_COMPILER_OPTIMIZING_SCHEDULER_ARM_H_
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#include "code_generator_arm_vixl.h"
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#include "scheduler.h"
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namespace art {
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namespace arm {
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// TODO: Replace CodeGeneratorARMType with CodeGeneratorARMVIXL everywhere?
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typedef CodeGeneratorARMVIXL CodeGeneratorARMType;
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// AArch32 instruction latencies.
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// We currently assume that all ARM CPUs share the same instruction latency list.
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// The following latencies were tuned based on performance experiments and
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// automatic tuning using differential evolution approach on various benchmarks.
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static constexpr uint32_t kArmIntegerOpLatency = 2;
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static constexpr uint32_t kArmFloatingPointOpLatency = 11;
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static constexpr uint32_t kArmDataProcWithShifterOpLatency = 4;
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static constexpr uint32_t kArmMulIntegerLatency = 6;
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static constexpr uint32_t kArmMulFloatingPointLatency = 11;
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static constexpr uint32_t kArmDivIntegerLatency = 10;
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static constexpr uint32_t kArmDivFloatLatency = 20;
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static constexpr uint32_t kArmDivDoubleLatency = 25;
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static constexpr uint32_t kArmTypeConversionFloatingPointIntegerLatency = 11;
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static constexpr uint32_t kArmMemoryLoadLatency = 9;
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static constexpr uint32_t kArmMemoryStoreLatency = 9;
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static constexpr uint32_t kArmMemoryBarrierLatency = 6;
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static constexpr uint32_t kArmBranchLatency = 4;
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static constexpr uint32_t kArmCallLatency = 5;
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static constexpr uint32_t kArmCallInternalLatency = 29;
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static constexpr uint32_t kArmLoadStringInternalLatency = 10;
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static constexpr uint32_t kArmNopLatency = 2;
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static constexpr uint32_t kArmLoadWithBakerReadBarrierLatency = 18;
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static constexpr uint32_t kArmRuntimeTypeCheckLatency = 46;
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class SchedulingLatencyVisitorARM : public SchedulingLatencyVisitor {
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public:
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explicit SchedulingLatencyVisitorARM(CodeGenerator* codegen)
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: codegen_(down_cast<CodeGeneratorARMType*>(codegen)) {}
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// Default visitor for instructions not handled specifically below.
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void VisitInstruction(HInstruction* ATTRIBUTE_UNUSED) {
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last_visited_latency_ = kArmIntegerOpLatency;
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}
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// We add a second unused parameter to be able to use this macro like the others
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// defined in `nodes.h`.
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#define FOR_EACH_SCHEDULED_ARM_INSTRUCTION(M) \
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M(ArrayGet , unused) \
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M(ArrayLength , unused) \
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M(ArraySet , unused) \
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M(Add , unused) \
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M(Sub , unused) \
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M(And , unused) \
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M(Or , unused) \
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M(Ror , unused) \
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M(Xor , unused) \
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M(Shl , unused) \
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M(Shr , unused) \
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M(UShr , unused) \
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M(Mul , unused) \
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M(Div , unused) \
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M(Condition , unused) \
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M(Compare , unused) \
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M(BoundsCheck , unused) \
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M(InstanceFieldGet , unused) \
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M(InstanceFieldSet , unused) \
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M(InstanceOf , unused) \
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M(Invoke , unused) \
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M(LoadString , unused) \
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M(NewArray , unused) \
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M(NewInstance , unused) \
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M(Rem , unused) \
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M(StaticFieldGet , unused) \
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M(StaticFieldSet , unused) \
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M(SuspendCheck , unused) \
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M(TypeConversion , unused)
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#define FOR_EACH_SCHEDULED_SHARED_INSTRUCTION(M) \
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M(BitwiseNegatedRight, unused) \
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M(MultiplyAccumulate, unused) \
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M(IntermediateAddress, unused) \
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M(IntermediateAddressIndex, unused) \
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M(DataProcWithShifterOp, unused)
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#define DECLARE_VISIT_INSTRUCTION(type, unused) \
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void Visit##type(H##type* instruction) OVERRIDE;
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FOR_EACH_SCHEDULED_ARM_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_SCHEDULED_SHARED_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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private:
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void HandleBinaryOperationLantencies(HBinaryOperation* instr);
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void HandleBitwiseOperationLantencies(HBinaryOperation* instr);
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void HandleShiftLatencies(HBinaryOperation* instr);
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void HandleDivRemConstantIntegralLatencies(int32_t imm);
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void HandleFieldSetLatencies(HInstruction* instruction, const FieldInfo& field_info);
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void HandleFieldGetLatencies(HInstruction* instruction, const FieldInfo& field_info);
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void HandleGenerateDataProcInstruction(bool internal_latency = false);
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void HandleGenerateDataProc(HDataProcWithShifterOp* instruction);
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void HandleGenerateLongDataProc(HDataProcWithShifterOp* instruction);
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// The latency setting for each HInstruction depends on how CodeGenerator may generate code,
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// latency visitors may query CodeGenerator for such information for accurate latency settings.
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CodeGeneratorARMType* codegen_;
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};
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class HSchedulerARM : public HScheduler {
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public:
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HSchedulerARM(ArenaAllocator* arena,
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SchedulingNodeSelector* selector,
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SchedulingLatencyVisitorARM* arm_latency_visitor)
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: HScheduler(arena, arm_latency_visitor, selector) {}
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~HSchedulerARM() OVERRIDE {}
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bool IsSchedulable(const HInstruction* instruction) const OVERRIDE {
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#define CASE_INSTRUCTION_KIND(type, unused) case \
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HInstruction::InstructionKind::k##type:
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switch (instruction->GetKind()) {
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FOR_EACH_SCHEDULED_SHARED_INSTRUCTION(CASE_INSTRUCTION_KIND)
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return true;
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FOR_EACH_CONCRETE_INSTRUCTION_ARM(CASE_INSTRUCTION_KIND)
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return true;
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default:
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return HScheduler::IsSchedulable(instruction);
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}
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#undef CASE_INSTRUCTION_KIND
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(HSchedulerARM);
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};
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} // namespace arm
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} // namespace art
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#endif // ART_COMPILER_OPTIMIZING_SCHEDULER_ARM_H_
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