401 lines
9.5 KiB
ArmAsm
401 lines
9.5 KiB
ArmAsm
/*
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* Copyright (c) 2017 Imagination Technologies.
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer
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* in the documentation and/or other materials provided with
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* the distribution.
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* * Neither the name of Imagination Technologies nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef __ANDROID__
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# include <private/bionic_asm.h>
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#elif _LIBC
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# include <sysdep.h>
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# include <regdef.h>
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# include <sys/asm.h>
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#elif _COMPILING_NEWLIB
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# include "machine/asm.h"
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# include "machine/regdef.h"
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#else
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# include <regdef.h>
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# include <sys/asm.h>
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#endif
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#if __mips64
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# define NSIZE 8
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# define LW ld
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# define LWR ldr
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# define LWL ldl
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# define EXT dext
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# define SRL dsrl
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# define SUBU dsubu
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#else
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# define NSIZE 4
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# define LW lw
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# define LWR lwr
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# define LWL lwl
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# define EXT ext
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# define SRL srl
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# define SUBU subu
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#endif
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/* Technically strcmp should not read past the end of the strings being
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compared. We will read a full word that may contain excess bits beyond
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the NULL string terminator but unless ENABLE_READAHEAD is set, we will not
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read the next word after the end of string. Setting ENABLE_READAHEAD will
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improve performance but is technically illegal based on the definition of
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strcmp. */
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#ifdef ENABLE_READAHEAD
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# define DELAY_READ
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#else
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# define DELAY_READ nop
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#endif
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/* Testing on a little endian machine showed using CLZ was a
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performance loss, so we are not turning it on by default. */
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#if defined(ENABLE_CLZ) && (__mips_isa_rev > 1) && (!__mips64)
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# define USE_CLZ
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#endif
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/* Some asm.h files do not have the L macro definition. */
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#ifndef L
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# if _MIPS_SIM == _ABIO32
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# define L(label) $L ## label
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# else
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# define L(label) .L ## label
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# endif
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#endif
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/* Some asm.h files do not have the PTR_ADDIU macro definition. */
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#ifndef PTR_ADDIU
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# if _MIPS_SIM == _ABIO32
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# define PTR_ADDIU addiu
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# else
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# define PTR_ADDIU daddiu
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# endif
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#endif
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/* It might seem better to do the 'beq' instruction between the two 'lbu'
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instructions so that the nop is not needed but testing showed that this
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code is actually faster (based on glibc strcmp test). */
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#define BYTECMP01(OFFSET) \
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lbu v0, OFFSET(a0); \
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lbu v1, OFFSET(a1); \
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beq v0, zero, L(bexit01); \
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nop; \
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bne v0, v1, L(bexit01)
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#define BYTECMP89(OFFSET) \
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lbu t8, OFFSET(a0); \
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lbu t9, OFFSET(a1); \
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beq t8, zero, L(bexit89); \
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nop; \
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bne t8, t9, L(bexit89)
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/* Allow the routine to be named something else if desired. */
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#ifndef STRNCMP_NAME
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# define STRNCMP_NAME strncmp
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#endif
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#ifdef __ANDROID__
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LEAF(STRNCMP_NAME, 0)
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#else
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LEAF(STRNCMP_NAME)
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#endif
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.set nomips16
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.set noreorder
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srl t0, a2, (2 + NSIZE / 4)
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beqz t0, L(byteloop) #process by bytes if less than (2 * NSIZE)
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andi t1, a1, (NSIZE - 1)
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beqz t1, L(exitalign)
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or t0, zero, NSIZE
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SUBU t1, t0, t1 #process (NSIZE - 1) bytes at max
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SUBU a2, a2, t1 #dec count by t1
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L(alignloop): #do by bytes until a1 aligned
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BYTECMP01(0)
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SUBU t1, t1, 0x1
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PTR_ADDIU a0, a0, 0x1
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bne t1, zero, L(alignloop)
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PTR_ADDIU a1, a1, 0x1
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L(exitalign):
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/* string a1 is NSIZE byte aligned at this point. */
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#ifndef __mips1
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lui t8, 0x0101
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ori t8, 0x0101
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lui t9, 0x7f7f
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ori t9, 0x7f7f
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#if __mips64
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dsll t0, t8, 32
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or t8, t0
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dsll t1, t9, 32
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or t9, t1
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#endif
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#endif
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/* hardware or software alignment not supported for mips1
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rev6 archs have h/w unaligned support
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remainings archs need to implemented with unaligned instructions */
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#if __mips1
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andi t0, a0, (NSIZE - 1)
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bne t0, zero, L(byteloop)
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#elif __mips_isa_rev < 6
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andi t0, a0, (NSIZE - 1)
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bne t0, zero, L(uwordloop)
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#endif
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#define STRCMPW(OFFSET) \
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LW v0, (OFFSET)(a0); \
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LW v1, (OFFSET)(a1); \
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SUBU t0, v0, t8; \
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bne v0, v1, L(worddiff); \
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nor t1, v0, t9; \
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and t0, t0, t1; \
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bne t0, zero, L(returnzero);\
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L(wordloop):
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SUBU t1, a2, (8 * NSIZE)
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bltz t1, L(onewords)
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STRCMPW(0 * NSIZE)
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DELAY_READ
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STRCMPW(1 * NSIZE)
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DELAY_READ
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STRCMPW(2 * NSIZE)
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DELAY_READ
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STRCMPW(3 * NSIZE)
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DELAY_READ
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STRCMPW(4 * NSIZE)
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DELAY_READ
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STRCMPW(5 * NSIZE)
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DELAY_READ
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STRCMPW(6 * NSIZE)
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DELAY_READ
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STRCMPW(7 * NSIZE)
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SUBU a2, a2, (8 * NSIZE)
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PTR_ADDIU a0, a0, (8 * NSIZE)
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b L(wordloop)
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PTR_ADDIU a1, a1, (8 * NSIZE)
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L(onewords):
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SUBU t1, a2, NSIZE
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bltz t1, L(byteloop)
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STRCMPW(0)
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SUBU a2, a2, NSIZE
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PTR_ADDIU a0, a0, NSIZE
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b L(onewords)
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PTR_ADDIU a1, a1, NSIZE
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#if __mips_isa_rev < 6 && !__mips1
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#define USTRCMPW(OFFSET) \
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LWR v0, (OFFSET)(a0); \
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LWL v0, (OFFSET + NSIZE - 1)(a0); \
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LW v1, (OFFSET)(a1); \
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SUBU t0, v0, t8; \
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bne v0, v1, L(worddiff); \
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nor t1, v0, t9; \
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and t0, t0, t1; \
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bne t0, zero, L(returnzero);\
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L(uwordloop):
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SUBU t1, a2, (8 * NSIZE)
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bltz t1, L(uonewords)
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USTRCMPW(0 * NSIZE)
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DELAY_READ
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USTRCMPW(1 * NSIZE)
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DELAY_READ
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USTRCMPW(2 * NSIZE)
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DELAY_READ
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USTRCMPW(3 * NSIZE)
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DELAY_READ
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USTRCMPW(4 * NSIZE)
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DELAY_READ
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USTRCMPW(5 * NSIZE)
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DELAY_READ
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USTRCMPW(6 * NSIZE)
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DELAY_READ
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USTRCMPW(7 * NSIZE)
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SUBU a2, a2, (8 * NSIZE)
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PTR_ADDIU a0, a0, (8 * NSIZE)
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b L(uwordloop)
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PTR_ADDIU a1, a1, (8 * NSIZE)
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L(uonewords):
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SUBU t1, a2, NSIZE
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bltz t1, L(byteloop)
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USTRCMPW(0)
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SUBU a2, a2, NSIZE
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PTR_ADDIU a0, a0, NSIZE
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b L(uonewords)
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PTR_ADDIU a1, a1, NSIZE
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#endif
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L(returnzero):
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j ra
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move v0, zero
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#if __mips_isa_rev > 1
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#define EXT_COMPARE01(POS) \
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EXT t0, v0, POS, 8; \
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beq t0, zero, L(wexit01); \
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EXT t1, v1, POS, 8; \
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bne t0, t1, L(wexit01)
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#define EXT_COMPARE89(POS) \
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EXT t8, v0, POS, 8; \
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beq t8, zero, L(wexit89); \
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EXT t9, v1, POS, 8; \
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bne t8, t9, L(wexit89)
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#else
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#define EXT_COMPARE01(POS) \
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SRL t0, v0, POS; \
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SRL t1, v1, POS; \
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andi t0, t0, 0xff; \
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beq t0, zero, L(wexit01); \
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andi t1, t1, 0xff; \
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bne t0, t1, L(wexit01)
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#define EXT_COMPARE89(POS) \
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SRL t8, v0, POS; \
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SRL t9, v1, POS; \
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andi t8, t8, 0xff; \
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beq t8, zero, L(wexit89); \
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andi t9, t9, 0xff; \
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bne t8, t9, L(wexit89)
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#endif
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L(worddiff):
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#ifdef USE_CLZ
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SUBU t0, v0, t8
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nor t1, v0, t9
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and t1, t0, t1
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xor t0, v0, v1
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or t0, t0, t1
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# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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wsbh t0, t0
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rotr t0, t0, 16
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# endif
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clz t1, t0
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and t1, 0xf8
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# if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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neg t1
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addu t1, 24
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# endif
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rotrv v0, v0, t1
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rotrv v1, v1, t1
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and v0, v0, 0xff
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and v1, v1, 0xff
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j ra
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SUBU v0, v0, v1
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#else /* USE_CLZ */
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# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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andi t0, v0, 0xff
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beq t0, zero, L(wexit01)
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andi t1, v1, 0xff
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bne t0, t1, L(wexit01)
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EXT_COMPARE89(8)
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EXT_COMPARE01(16)
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#ifndef __mips64
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SRL t8, v0, 24
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SRL t9, v1, 24
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#else
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EXT_COMPARE89(24)
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EXT_COMPARE01(32)
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EXT_COMPARE89(40)
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EXT_COMPARE01(48)
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SRL t8, v0, 56
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SRL t9, v1, 56
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#endif
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# else /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */
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#ifdef __mips64
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SRL t0, v0, 56
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beq t0, zero, L(wexit01)
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SRL t1, v1, 56
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bne t0, t1, L(wexit01)
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EXT_COMPARE89(48)
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EXT_COMPARE01(40)
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EXT_COMPARE89(32)
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EXT_COMPARE01(24)
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#else
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SRL t0, v0, 24
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beq t0, zero, L(wexit01)
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SRL t1, v1, 24
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bne t0, t1, L(wexit01)
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#endif
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EXT_COMPARE89(16)
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EXT_COMPARE01(8)
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andi t8, v0, 0xff
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andi t9, v1, 0xff
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# endif /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */
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L(wexit89):
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j ra
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SUBU v0, t8, t9
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L(wexit01):
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j ra
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SUBU v0, t0, t1
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#endif /* USE_CLZ */
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L(byteloop):
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beq a2, zero, L(returnzero)
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SUBU a2, a2, 1
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BYTECMP01(0)
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nop
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beq a2, zero, L(returnzero)
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SUBU a2, a2, 1
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BYTECMP89(1)
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nop
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beq a2, zero, L(returnzero)
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SUBU a2, a2, 1
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BYTECMP01(2)
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nop
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beq a2, zero, L(returnzero)
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SUBU a2, a2, 1
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BYTECMP89(3)
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PTR_ADDIU a0, a0, 4
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b L(byteloop)
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PTR_ADDIU a1, a1, 4
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L(bexit01):
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j ra
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SUBU v0, v0, v1
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L(bexit89):
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j ra
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SUBU v0, t8, t9
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.set at
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.set reorder
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END(STRNCMP_NAME)
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#ifndef __ANDROID__
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# ifdef _LIBC
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libc_hidden_builtin_def (STRNCMP_NAME)
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# endif
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#endif
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