832 lines
36 KiB
C++
832 lines
36 KiB
C++
/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM64_H_
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#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM64_H_
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#include "arch/arm64/quick_method_frame_info_arm64.h"
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#include "code_generator.h"
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#include "common_arm64.h"
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#include "dex_file_types.h"
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#include "driver/compiler_options.h"
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#include "nodes.h"
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#include "parallel_move_resolver.h"
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#include "string_reference.h"
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#include "type_reference.h"
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#include "utils/arm64/assembler_arm64.h"
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// TODO(VIXL): Make VIXL compile with -Wshadow.
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wshadow"
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#include "aarch64/disasm-aarch64.h"
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#include "aarch64/macro-assembler-aarch64.h"
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#pragma GCC diagnostic pop
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namespace art {
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namespace arm64 {
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class CodeGeneratorARM64;
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// Use a local definition to prevent copying mistakes.
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static constexpr size_t kArm64WordSize = static_cast<size_t>(kArm64PointerSize);
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// These constants are used as an approximate margin when emission of veneer and literal pools
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// must be blocked.
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static constexpr int kMaxMacroInstructionSizeInBytes = 15 * vixl::aarch64::kInstructionSize;
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static constexpr int kInvokeCodeMarginSizeInBytes = 6 * kMaxMacroInstructionSizeInBytes;
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static const vixl::aarch64::Register kParameterCoreRegisters[] = {
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vixl::aarch64::x1,
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vixl::aarch64::x2,
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vixl::aarch64::x3,
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vixl::aarch64::x4,
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vixl::aarch64::x5,
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vixl::aarch64::x6,
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vixl::aarch64::x7
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};
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static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
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static const vixl::aarch64::FPRegister kParameterFPRegisters[] = {
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vixl::aarch64::d0,
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vixl::aarch64::d1,
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vixl::aarch64::d2,
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vixl::aarch64::d3,
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vixl::aarch64::d4,
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vixl::aarch64::d5,
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vixl::aarch64::d6,
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vixl::aarch64::d7
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};
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static constexpr size_t kParameterFPRegistersLength = arraysize(kParameterFPRegisters);
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// Thread Register.
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const vixl::aarch64::Register tr = vixl::aarch64::x19;
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// Marking Register.
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const vixl::aarch64::Register mr = vixl::aarch64::x20;
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// Method register on invoke.
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static const vixl::aarch64::Register kArtMethodRegister = vixl::aarch64::x0;
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const vixl::aarch64::CPURegList vixl_reserved_core_registers(vixl::aarch64::ip0,
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vixl::aarch64::ip1);
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const vixl::aarch64::CPURegList vixl_reserved_fp_registers(vixl::aarch64::d31);
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const vixl::aarch64::CPURegList runtime_reserved_core_registers =
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vixl::aarch64::CPURegList(
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tr,
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// Reserve X20 as Marking Register when emitting Baker read barriers.
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((kEmitCompilerReadBarrier && kUseBakerReadBarrier) ? mr : vixl::aarch64::NoCPUReg),
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vixl::aarch64::lr);
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// Callee-save registers AAPCS64, without x19 (Thread Register) (nor
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// x20 (Marking Register) when emitting Baker read barriers).
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const vixl::aarch64::CPURegList callee_saved_core_registers(
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vixl::aarch64::CPURegister::kRegister,
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vixl::aarch64::kXRegSize,
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((kEmitCompilerReadBarrier && kUseBakerReadBarrier)
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? vixl::aarch64::x21.GetCode()
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: vixl::aarch64::x20.GetCode()),
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vixl::aarch64::x30.GetCode());
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const vixl::aarch64::CPURegList callee_saved_fp_registers(vixl::aarch64::CPURegister::kFPRegister,
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vixl::aarch64::kDRegSize,
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vixl::aarch64::d8.GetCode(),
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vixl::aarch64::d15.GetCode());
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Location ARM64ReturnLocation(Primitive::Type return_type);
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class SlowPathCodeARM64 : public SlowPathCode {
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public:
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explicit SlowPathCodeARM64(HInstruction* instruction)
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: SlowPathCode(instruction), entry_label_(), exit_label_() {}
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vixl::aarch64::Label* GetEntryLabel() { return &entry_label_; }
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vixl::aarch64::Label* GetExitLabel() { return &exit_label_; }
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void SaveLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) OVERRIDE;
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void RestoreLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) OVERRIDE;
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private:
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vixl::aarch64::Label entry_label_;
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vixl::aarch64::Label exit_label_;
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DISALLOW_COPY_AND_ASSIGN(SlowPathCodeARM64);
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};
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class JumpTableARM64 : public DeletableArenaObject<kArenaAllocSwitchTable> {
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public:
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explicit JumpTableARM64(HPackedSwitch* switch_instr)
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: switch_instr_(switch_instr), table_start_() {}
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vixl::aarch64::Label* GetTableStartLabel() { return &table_start_; }
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void EmitTable(CodeGeneratorARM64* codegen);
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private:
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HPackedSwitch* const switch_instr_;
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vixl::aarch64::Label table_start_;
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DISALLOW_COPY_AND_ASSIGN(JumpTableARM64);
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};
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static const vixl::aarch64::Register kRuntimeParameterCoreRegisters[] =
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{ vixl::aarch64::x0,
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vixl::aarch64::x1,
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vixl::aarch64::x2,
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vixl::aarch64::x3,
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vixl::aarch64::x4,
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vixl::aarch64::x5,
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vixl::aarch64::x6,
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vixl::aarch64::x7 };
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static constexpr size_t kRuntimeParameterCoreRegistersLength =
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arraysize(kRuntimeParameterCoreRegisters);
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static const vixl::aarch64::FPRegister kRuntimeParameterFpuRegisters[] =
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{ vixl::aarch64::d0,
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vixl::aarch64::d1,
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vixl::aarch64::d2,
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vixl::aarch64::d3,
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vixl::aarch64::d4,
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vixl::aarch64::d5,
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vixl::aarch64::d6,
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vixl::aarch64::d7 };
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static constexpr size_t kRuntimeParameterFpuRegistersLength =
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arraysize(kRuntimeParameterCoreRegisters);
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class InvokeRuntimeCallingConvention : public CallingConvention<vixl::aarch64::Register,
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vixl::aarch64::FPRegister> {
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public:
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static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
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InvokeRuntimeCallingConvention()
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: CallingConvention(kRuntimeParameterCoreRegisters,
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kRuntimeParameterCoreRegistersLength,
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kRuntimeParameterFpuRegisters,
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kRuntimeParameterFpuRegistersLength,
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kArm64PointerSize) {}
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Location GetReturnLocation(Primitive::Type return_type);
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConvention);
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};
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class InvokeDexCallingConvention : public CallingConvention<vixl::aarch64::Register,
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vixl::aarch64::FPRegister> {
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public:
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InvokeDexCallingConvention()
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: CallingConvention(kParameterCoreRegisters,
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kParameterCoreRegistersLength,
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kParameterFPRegisters,
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kParameterFPRegistersLength,
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kArm64PointerSize) {}
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Location GetReturnLocation(Primitive::Type return_type) const {
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return ARM64ReturnLocation(return_type);
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConvention);
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};
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class InvokeDexCallingConventionVisitorARM64 : public InvokeDexCallingConventionVisitor {
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public:
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InvokeDexCallingConventionVisitorARM64() {}
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virtual ~InvokeDexCallingConventionVisitorARM64() {}
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Location GetNextLocation(Primitive::Type type) OVERRIDE;
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Location GetReturnLocation(Primitive::Type return_type) const OVERRIDE {
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return calling_convention.GetReturnLocation(return_type);
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}
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Location GetMethodLocation() const OVERRIDE;
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private:
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InvokeDexCallingConvention calling_convention;
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorARM64);
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};
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class FieldAccessCallingConventionARM64 : public FieldAccessCallingConvention {
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public:
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FieldAccessCallingConventionARM64() {}
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Location GetObjectLocation() const OVERRIDE {
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return helpers::LocationFrom(vixl::aarch64::x1);
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}
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Location GetFieldIndexLocation() const OVERRIDE {
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return helpers::LocationFrom(vixl::aarch64::x0);
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}
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Location GetReturnLocation(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE {
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return helpers::LocationFrom(vixl::aarch64::x0);
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}
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Location GetSetValueLocation(Primitive::Type type ATTRIBUTE_UNUSED,
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bool is_instance) const OVERRIDE {
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return is_instance
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? helpers::LocationFrom(vixl::aarch64::x2)
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: helpers::LocationFrom(vixl::aarch64::x1);
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}
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Location GetFpuLocation(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE {
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return helpers::LocationFrom(vixl::aarch64::d0);
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionARM64);
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};
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class InstructionCodeGeneratorARM64 : public InstructionCodeGenerator {
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public:
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InstructionCodeGeneratorARM64(HGraph* graph, CodeGeneratorARM64* codegen);
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) OVERRIDE;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_ARM64(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) OVERRIDE {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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Arm64Assembler* GetAssembler() const { return assembler_; }
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vixl::aarch64::MacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); }
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private:
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void GenerateClassInitializationCheck(SlowPathCodeARM64* slow_path,
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vixl::aarch64::Register class_reg);
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void GenerateSuspendCheck(HSuspendCheck* instruction, HBasicBlock* successor);
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void HandleBinaryOp(HBinaryOperation* instr);
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void HandleFieldSet(HInstruction* instruction,
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const FieldInfo& field_info,
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bool value_can_be_null);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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void HandleCondition(HCondition* instruction);
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// Generate a heap reference load using one register `out`:
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//
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// out <- *(out + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a read barrier and
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// shall be a register in that case; it may be an invalid location
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// otherwise.
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void GenerateReferenceLoadOneRegister(HInstruction* instruction,
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Location out,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a heap reference load using two different registers
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// `out` and `obj`:
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//
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// out <- *(obj + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a Baker's (fast
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// path) read barrier and shall be a register in that case; it may
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// be an invalid location otherwise.
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void GenerateReferenceLoadTwoRegisters(HInstruction* instruction,
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Location out,
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Location obj,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a GC root reference load:
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//
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// root <- *(obj + offset)
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//
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// while honoring read barriers based on read_barrier_option.
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void GenerateGcRootFieldLoad(HInstruction* instruction,
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Location root,
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vixl::aarch64::Register obj,
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uint32_t offset,
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vixl::aarch64::Label* fixup_label,
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ReadBarrierOption read_barrier_option);
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// Generate a floating-point comparison.
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void GenerateFcmp(HInstruction* instruction);
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void HandleShift(HBinaryOperation* instr);
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void GenerateTestAndBranch(HInstruction* instruction,
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size_t condition_input_index,
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vixl::aarch64::Label* true_target,
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vixl::aarch64::Label* false_target);
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void DivRemOneOrMinusOne(HBinaryOperation* instruction);
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void DivRemByPowerOfTwo(HBinaryOperation* instruction);
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void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction);
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void GenerateDivRemIntegral(HBinaryOperation* instruction);
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void HandleGoto(HInstruction* got, HBasicBlock* successor);
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vixl::aarch64::MemOperand VecAddress(
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HVecMemoryOperation* instruction,
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// This function may acquire a scratch register.
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vixl::aarch64::UseScratchRegisterScope* temps_scope,
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size_t size,
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bool is_string_char_at,
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/*out*/ vixl::aarch64::Register* scratch);
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Arm64Assembler* const assembler_;
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CodeGeneratorARM64* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorARM64);
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};
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class LocationsBuilderARM64 : public HGraphVisitor {
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public:
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LocationsBuilderARM64(HGraph* graph, CodeGeneratorARM64* codegen)
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: HGraphVisitor(graph), codegen_(codegen) {}
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) OVERRIDE;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_ARM64(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) OVERRIDE {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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private:
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void HandleBinaryOp(HBinaryOperation* instr);
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void HandleFieldSet(HInstruction* instruction);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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void HandleInvoke(HInvoke* instr);
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void HandleCondition(HCondition* instruction);
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void HandleShift(HBinaryOperation* instr);
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CodeGeneratorARM64* const codegen_;
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InvokeDexCallingConventionVisitorARM64 parameter_visitor_;
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DISALLOW_COPY_AND_ASSIGN(LocationsBuilderARM64);
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};
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class ParallelMoveResolverARM64 : public ParallelMoveResolverNoSwap {
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public:
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ParallelMoveResolverARM64(ArenaAllocator* allocator, CodeGeneratorARM64* codegen)
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: ParallelMoveResolverNoSwap(allocator), codegen_(codegen), vixl_temps_() {}
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protected:
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void PrepareForEmitNativeCode() OVERRIDE;
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void FinishEmitNativeCode() OVERRIDE;
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Location AllocateScratchLocationFor(Location::Kind kind) OVERRIDE;
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void FreeScratchLocation(Location loc) OVERRIDE;
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void EmitMove(size_t index) OVERRIDE;
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private:
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Arm64Assembler* GetAssembler() const;
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vixl::aarch64::MacroAssembler* GetVIXLAssembler() const {
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return GetAssembler()->GetVIXLAssembler();
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}
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CodeGeneratorARM64* const codegen_;
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vixl::aarch64::UseScratchRegisterScope vixl_temps_;
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DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverARM64);
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};
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class CodeGeneratorARM64 : public CodeGenerator {
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public:
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CodeGeneratorARM64(HGraph* graph,
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const Arm64InstructionSetFeatures& isa_features,
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const CompilerOptions& compiler_options,
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OptimizingCompilerStats* stats = nullptr);
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virtual ~CodeGeneratorARM64() {}
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void GenerateFrameEntry() OVERRIDE;
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void GenerateFrameExit() OVERRIDE;
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vixl::aarch64::CPURegList GetFramePreservedCoreRegisters() const;
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vixl::aarch64::CPURegList GetFramePreservedFPRegisters() const;
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void Bind(HBasicBlock* block) OVERRIDE;
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vixl::aarch64::Label* GetLabelOf(HBasicBlock* block) {
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block = FirstNonEmptyBlock(block);
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return &(block_labels_[block->GetBlockId()]);
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}
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size_t GetWordSize() const OVERRIDE {
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return kArm64WordSize;
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}
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size_t GetFloatingPointSpillSlotSize() const OVERRIDE {
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return GetGraph()->HasSIMD()
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? 2 * kArm64WordSize // 16 bytes == 2 arm64 words for each spill
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: 1 * kArm64WordSize; // 8 bytes == 1 arm64 words for each spill
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}
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uintptr_t GetAddressOf(HBasicBlock* block) OVERRIDE {
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vixl::aarch64::Label* block_entry_label = GetLabelOf(block);
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DCHECK(block_entry_label->IsBound());
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return block_entry_label->GetLocation();
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}
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HGraphVisitor* GetLocationBuilder() OVERRIDE { return &location_builder_; }
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HGraphVisitor* GetInstructionVisitor() OVERRIDE { return &instruction_visitor_; }
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Arm64Assembler* GetAssembler() OVERRIDE { return &assembler_; }
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const Arm64Assembler& GetAssembler() const OVERRIDE { return assembler_; }
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vixl::aarch64::MacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); }
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// Emit a write barrier.
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void MarkGCCard(vixl::aarch64::Register object,
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vixl::aarch64::Register value,
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bool value_can_be_null);
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void GenerateMemoryBarrier(MemBarrierKind kind);
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// Register allocation.
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void SetupBlockedRegisters() const OVERRIDE;
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size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
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size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
|
|
size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
|
|
size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
|
|
|
|
// The number of registers that can be allocated. The register allocator may
|
|
// decide to reserve and not use a few of them.
|
|
// We do not consider registers sp, xzr, wzr. They are either not allocatable
|
|
// (xzr, wzr), or make for poor allocatable registers (sp alignment
|
|
// requirements, etc.). This also facilitates our task as all other registers
|
|
// can easily be mapped via to or from their type and index or code.
|
|
static const int kNumberOfAllocatableRegisters = vixl::aarch64::kNumberOfRegisters - 1;
|
|
static const int kNumberOfAllocatableFPRegisters = vixl::aarch64::kNumberOfFPRegisters;
|
|
static constexpr int kNumberOfAllocatableRegisterPairs = 0;
|
|
|
|
void DumpCoreRegister(std::ostream& stream, int reg) const OVERRIDE;
|
|
void DumpFloatingPointRegister(std::ostream& stream, int reg) const OVERRIDE;
|
|
|
|
InstructionSet GetInstructionSet() const OVERRIDE {
|
|
return InstructionSet::kArm64;
|
|
}
|
|
|
|
const Arm64InstructionSetFeatures& GetInstructionSetFeatures() const {
|
|
return isa_features_;
|
|
}
|
|
|
|
void Initialize() OVERRIDE {
|
|
block_labels_.resize(GetGraph()->GetBlocks().size());
|
|
}
|
|
|
|
// We want to use the STP and LDP instructions to spill and restore registers for slow paths.
|
|
// These instructions can only encode offsets that are multiples of the register size accessed.
|
|
uint32_t GetPreferredSlotsAlignment() const OVERRIDE { return vixl::aarch64::kXRegSizeInBytes; }
|
|
|
|
JumpTableARM64* CreateJumpTable(HPackedSwitch* switch_instr) {
|
|
jump_tables_.emplace_back(new (GetGraph()->GetArena()) JumpTableARM64(switch_instr));
|
|
return jump_tables_.back().get();
|
|
}
|
|
|
|
void Finalize(CodeAllocator* allocator) OVERRIDE;
|
|
|
|
// Code generation helpers.
|
|
void MoveConstant(vixl::aarch64::CPURegister destination, HConstant* constant);
|
|
void MoveConstant(Location destination, int32_t value) OVERRIDE;
|
|
void MoveLocation(Location dst, Location src, Primitive::Type dst_type) OVERRIDE;
|
|
void AddLocationAsTemp(Location location, LocationSummary* locations) OVERRIDE;
|
|
|
|
void Load(Primitive::Type type,
|
|
vixl::aarch64::CPURegister dst,
|
|
const vixl::aarch64::MemOperand& src);
|
|
void Store(Primitive::Type type,
|
|
vixl::aarch64::CPURegister src,
|
|
const vixl::aarch64::MemOperand& dst);
|
|
void LoadAcquire(HInstruction* instruction,
|
|
vixl::aarch64::CPURegister dst,
|
|
const vixl::aarch64::MemOperand& src,
|
|
bool needs_null_check);
|
|
void StoreRelease(HInstruction* instruction,
|
|
Primitive::Type type,
|
|
vixl::aarch64::CPURegister src,
|
|
const vixl::aarch64::MemOperand& dst,
|
|
bool needs_null_check);
|
|
|
|
// Generate code to invoke a runtime entry point.
|
|
void InvokeRuntime(QuickEntrypointEnum entrypoint,
|
|
HInstruction* instruction,
|
|
uint32_t dex_pc,
|
|
SlowPathCode* slow_path = nullptr) OVERRIDE;
|
|
|
|
// Generate code to invoke a runtime entry point, but do not record
|
|
// PC-related information in a stack map.
|
|
void InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset,
|
|
HInstruction* instruction,
|
|
SlowPathCode* slow_path);
|
|
|
|
ParallelMoveResolverARM64* GetMoveResolver() OVERRIDE { return &move_resolver_; }
|
|
|
|
bool NeedsTwoRegisters(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE {
|
|
return false;
|
|
}
|
|
|
|
// Check if the desired_string_load_kind is supported. If it is, return it,
|
|
// otherwise return a fall-back kind that should be used instead.
|
|
HLoadString::LoadKind GetSupportedLoadStringKind(
|
|
HLoadString::LoadKind desired_string_load_kind) OVERRIDE;
|
|
|
|
// Check if the desired_class_load_kind is supported. If it is, return it,
|
|
// otherwise return a fall-back kind that should be used instead.
|
|
HLoadClass::LoadKind GetSupportedLoadClassKind(
|
|
HLoadClass::LoadKind desired_class_load_kind) OVERRIDE;
|
|
|
|
// Check if the desired_dispatch_info is supported. If it is, return it,
|
|
// otherwise return a fall-back info that should be used instead.
|
|
HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch(
|
|
const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info,
|
|
HInvokeStaticOrDirect* invoke) OVERRIDE;
|
|
|
|
void GenerateStaticOrDirectCall(
|
|
HInvokeStaticOrDirect* invoke, Location temp, SlowPathCode* slow_path = nullptr) OVERRIDE;
|
|
void GenerateVirtualCall(
|
|
HInvokeVirtual* invoke, Location temp, SlowPathCode* slow_path = nullptr) OVERRIDE;
|
|
|
|
void MoveFromReturnRegister(Location trg ATTRIBUTE_UNUSED,
|
|
Primitive::Type type ATTRIBUTE_UNUSED) OVERRIDE {
|
|
UNIMPLEMENTED(FATAL);
|
|
}
|
|
|
|
// Add a new PC-relative method patch for an instruction and return the label
|
|
// to be bound before the instruction. The instruction will be either the
|
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
|
// to the associated ADRP patch label).
|
|
vixl::aarch64::Label* NewPcRelativeMethodPatch(MethodReference target_method,
|
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
|
|
// Add a new .bss entry method patch for an instruction and return
|
|
// the label to be bound before the instruction. The instruction will be
|
|
// either the ADRP (pass `adrp_label = null`) or the LDR (pass `adrp_label`
|
|
// pointing to the associated ADRP patch label).
|
|
vixl::aarch64::Label* NewMethodBssEntryPatch(MethodReference target_method,
|
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
|
|
// Add a new PC-relative type patch for an instruction and return the label
|
|
// to be bound before the instruction. The instruction will be either the
|
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
|
// to the associated ADRP patch label).
|
|
vixl::aarch64::Label* NewPcRelativeTypePatch(const DexFile& dex_file,
|
|
dex::TypeIndex type_index,
|
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
|
|
// Add a new .bss entry type patch for an instruction and return the label
|
|
// to be bound before the instruction. The instruction will be either the
|
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
|
// to the associated ADRP patch label).
|
|
vixl::aarch64::Label* NewBssEntryTypePatch(const DexFile& dex_file,
|
|
dex::TypeIndex type_index,
|
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
|
|
// Add a new PC-relative string patch for an instruction and return the label
|
|
// to be bound before the instruction. The instruction will be either the
|
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
|
// to the associated ADRP patch label).
|
|
vixl::aarch64::Label* NewPcRelativeStringPatch(const DexFile& dex_file,
|
|
dex::StringIndex string_index,
|
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
|
|
// Add a new baker read barrier patch and return the label to be bound
|
|
// before the CBNZ instruction.
|
|
vixl::aarch64::Label* NewBakerReadBarrierPatch(uint32_t custom_data);
|
|
|
|
vixl::aarch64::Literal<uint32_t>* DeduplicateBootImageAddressLiteral(uint64_t address);
|
|
vixl::aarch64::Literal<uint32_t>* DeduplicateJitStringLiteral(const DexFile& dex_file,
|
|
dex::StringIndex string_index,
|
|
Handle<mirror::String> handle);
|
|
vixl::aarch64::Literal<uint32_t>* DeduplicateJitClassLiteral(const DexFile& dex_file,
|
|
dex::TypeIndex string_index,
|
|
Handle<mirror::Class> handle);
|
|
|
|
void EmitAdrpPlaceholder(vixl::aarch64::Label* fixup_label, vixl::aarch64::Register reg);
|
|
void EmitAddPlaceholder(vixl::aarch64::Label* fixup_label,
|
|
vixl::aarch64::Register out,
|
|
vixl::aarch64::Register base);
|
|
void EmitLdrOffsetPlaceholder(vixl::aarch64::Label* fixup_label,
|
|
vixl::aarch64::Register out,
|
|
vixl::aarch64::Register base);
|
|
|
|
void EmitLinkerPatches(ArenaVector<LinkerPatch>* linker_patches) OVERRIDE;
|
|
|
|
void EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) OVERRIDE;
|
|
|
|
// Fast path implementation of ReadBarrier::Barrier for a heap
|
|
// reference field load when Baker's read barriers are used.
|
|
void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction,
|
|
Location ref,
|
|
vixl::aarch64::Register obj,
|
|
uint32_t offset,
|
|
Location maybe_temp,
|
|
bool needs_null_check,
|
|
bool use_load_acquire);
|
|
// Fast path implementation of ReadBarrier::Barrier for a heap
|
|
// reference array load when Baker's read barriers are used.
|
|
void GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction,
|
|
Location ref,
|
|
vixl::aarch64::Register obj,
|
|
uint32_t data_offset,
|
|
Location index,
|
|
vixl::aarch64::Register temp,
|
|
bool needs_null_check);
|
|
// Factored implementation, used by GenerateFieldLoadWithBakerReadBarrier,
|
|
// GenerateArrayLoadWithBakerReadBarrier and some intrinsics.
|
|
//
|
|
// Load the object reference located at the address
|
|
// `obj + offset + (index << scale_factor)`, held by object `obj`, into
|
|
// `ref`, and mark it if needed.
|
|
void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction,
|
|
Location ref,
|
|
vixl::aarch64::Register obj,
|
|
uint32_t offset,
|
|
Location index,
|
|
size_t scale_factor,
|
|
vixl::aarch64::Register temp,
|
|
bool needs_null_check,
|
|
bool use_load_acquire);
|
|
|
|
// Generate code checking whether the the reference field at the
|
|
// address `obj + field_offset`, held by object `obj`, needs to be
|
|
// marked, and if so, marking it and updating the field within `obj`
|
|
// with the marked value.
|
|
//
|
|
// This routine is used for the implementation of the
|
|
// UnsafeCASObject intrinsic with Baker read barriers.
|
|
//
|
|
// This method has a structure similar to
|
|
// GenerateReferenceLoadWithBakerReadBarrier, but note that argument
|
|
// `ref` is only as a temporary here, and thus its value should not
|
|
// be used afterwards.
|
|
void UpdateReferenceFieldWithBakerReadBarrier(HInstruction* instruction,
|
|
Location ref,
|
|
vixl::aarch64::Register obj,
|
|
Location field_offset,
|
|
vixl::aarch64::Register temp,
|
|
bool needs_null_check,
|
|
bool use_load_acquire);
|
|
|
|
// Generate a heap reference load (with no read barrier).
|
|
void GenerateRawReferenceLoad(HInstruction* instruction,
|
|
Location ref,
|
|
vixl::aarch64::Register obj,
|
|
uint32_t offset,
|
|
Location index,
|
|
size_t scale_factor,
|
|
bool needs_null_check,
|
|
bool use_load_acquire);
|
|
|
|
// Generate a read barrier for a heap reference within `instruction`
|
|
// using a slow path.
|
|
//
|
|
// A read barrier for an object reference read from the heap is
|
|
// implemented as a call to the artReadBarrierSlow runtime entry
|
|
// point, which is passed the values in locations `ref`, `obj`, and
|
|
// `offset`:
|
|
//
|
|
// mirror::Object* artReadBarrierSlow(mirror::Object* ref,
|
|
// mirror::Object* obj,
|
|
// uint32_t offset);
|
|
//
|
|
// The `out` location contains the value returned by
|
|
// artReadBarrierSlow.
|
|
//
|
|
// When `index` is provided (i.e. for array accesses), the offset
|
|
// value passed to artReadBarrierSlow is adjusted to take `index`
|
|
// into account.
|
|
void GenerateReadBarrierSlow(HInstruction* instruction,
|
|
Location out,
|
|
Location ref,
|
|
Location obj,
|
|
uint32_t offset,
|
|
Location index = Location::NoLocation());
|
|
|
|
// If read barriers are enabled, generate a read barrier for a heap
|
|
// reference using a slow path. If heap poisoning is enabled, also
|
|
// unpoison the reference in `out`.
|
|
void MaybeGenerateReadBarrierSlow(HInstruction* instruction,
|
|
Location out,
|
|
Location ref,
|
|
Location obj,
|
|
uint32_t offset,
|
|
Location index = Location::NoLocation());
|
|
|
|
// Generate a read barrier for a GC root within `instruction` using
|
|
// a slow path.
|
|
//
|
|
// A read barrier for an object reference GC root is implemented as
|
|
// a call to the artReadBarrierForRootSlow runtime entry point,
|
|
// which is passed the value in location `root`:
|
|
//
|
|
// mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root);
|
|
//
|
|
// The `out` location contains the value returned by
|
|
// artReadBarrierForRootSlow.
|
|
void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root);
|
|
|
|
void GenerateNop() OVERRIDE;
|
|
|
|
void GenerateImplicitNullCheck(HNullCheck* instruction) OVERRIDE;
|
|
void GenerateExplicitNullCheck(HNullCheck* instruction) OVERRIDE;
|
|
|
|
private:
|
|
using Uint64ToLiteralMap = ArenaSafeMap<uint64_t, vixl::aarch64::Literal<uint64_t>*>;
|
|
using Uint32ToLiteralMap = ArenaSafeMap<uint32_t, vixl::aarch64::Literal<uint32_t>*>;
|
|
using StringToLiteralMap = ArenaSafeMap<StringReference,
|
|
vixl::aarch64::Literal<uint32_t>*,
|
|
StringReferenceValueComparator>;
|
|
using TypeToLiteralMap = ArenaSafeMap<TypeReference,
|
|
vixl::aarch64::Literal<uint32_t>*,
|
|
TypeReferenceValueComparator>;
|
|
|
|
vixl::aarch64::Literal<uint32_t>* DeduplicateUint32Literal(uint32_t value);
|
|
vixl::aarch64::Literal<uint64_t>* DeduplicateUint64Literal(uint64_t value);
|
|
|
|
// The PcRelativePatchInfo is used for PC-relative addressing of dex cache arrays
|
|
// and boot image strings/types. The only difference is the interpretation of the
|
|
// offset_or_index.
|
|
struct PcRelativePatchInfo {
|
|
PcRelativePatchInfo(const DexFile& dex_file, uint32_t off_or_idx)
|
|
: target_dex_file(dex_file), offset_or_index(off_or_idx), label(), pc_insn_label() { }
|
|
|
|
const DexFile& target_dex_file;
|
|
// Either the dex cache array element offset or the string/type index.
|
|
uint32_t offset_or_index;
|
|
vixl::aarch64::Label label;
|
|
vixl::aarch64::Label* pc_insn_label;
|
|
};
|
|
|
|
struct BakerReadBarrierPatchInfo {
|
|
explicit BakerReadBarrierPatchInfo(uint32_t data) : label(), custom_data(data) { }
|
|
|
|
vixl::aarch64::Label label;
|
|
uint32_t custom_data;
|
|
};
|
|
|
|
vixl::aarch64::Label* NewPcRelativePatch(const DexFile& dex_file,
|
|
uint32_t offset_or_index,
|
|
vixl::aarch64::Label* adrp_label,
|
|
ArenaDeque<PcRelativePatchInfo>* patches);
|
|
|
|
void EmitJumpTables();
|
|
|
|
template <LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)>
|
|
static void EmitPcRelativeLinkerPatches(const ArenaDeque<PcRelativePatchInfo>& infos,
|
|
ArenaVector<LinkerPatch>* linker_patches);
|
|
|
|
// Labels for each block that will be compiled.
|
|
// We use a deque so that the `vixl::aarch64::Label` objects do not move in memory.
|
|
ArenaDeque<vixl::aarch64::Label> block_labels_; // Indexed by block id.
|
|
vixl::aarch64::Label frame_entry_label_;
|
|
ArenaVector<std::unique_ptr<JumpTableARM64>> jump_tables_;
|
|
|
|
LocationsBuilderARM64 location_builder_;
|
|
InstructionCodeGeneratorARM64 instruction_visitor_;
|
|
ParallelMoveResolverARM64 move_resolver_;
|
|
Arm64Assembler assembler_;
|
|
const Arm64InstructionSetFeatures& isa_features_;
|
|
|
|
// Deduplication map for 32-bit literals, used for non-patchable boot image addresses.
|
|
Uint32ToLiteralMap uint32_literals_;
|
|
// Deduplication map for 64-bit literals, used for non-patchable method address or method code.
|
|
Uint64ToLiteralMap uint64_literals_;
|
|
// PC-relative method patch info for kBootImageLinkTimePcRelative.
|
|
ArenaDeque<PcRelativePatchInfo> pc_relative_method_patches_;
|
|
// PC-relative method patch info for kBssEntry.
|
|
ArenaDeque<PcRelativePatchInfo> method_bss_entry_patches_;
|
|
// PC-relative type patch info for kBootImageLinkTimePcRelative.
|
|
ArenaDeque<PcRelativePatchInfo> pc_relative_type_patches_;
|
|
// PC-relative type patch info for kBssEntry.
|
|
ArenaDeque<PcRelativePatchInfo> type_bss_entry_patches_;
|
|
// PC-relative String patch info; type depends on configuration (app .bss or boot image PIC).
|
|
ArenaDeque<PcRelativePatchInfo> pc_relative_string_patches_;
|
|
// Baker read barrier patch info.
|
|
ArenaDeque<BakerReadBarrierPatchInfo> baker_read_barrier_patches_;
|
|
|
|
// Patches for string literals in JIT compiled code.
|
|
StringToLiteralMap jit_string_patches_;
|
|
// Patches for class literals in JIT compiled code.
|
|
TypeToLiteralMap jit_class_patches_;
|
|
|
|
DISALLOW_COPY_AND_ASSIGN(CodeGeneratorARM64);
|
|
};
|
|
|
|
inline Arm64Assembler* ParallelMoveResolverARM64::GetAssembler() const {
|
|
return codegen_->GetAssembler();
|
|
}
|
|
|
|
} // namespace arm64
|
|
} // namespace art
|
|
|
|
#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM64_H_
|