30 lines
1.5 KiB
ArmAsm
30 lines
1.5 KiB
ArmAsm
%default {"preinstr":"", "result":"a0", "chkzero":"0"}
|
|
/*
|
|
* Generic 32-bit binary operation. Provide an "instr" line that
|
|
* specifies an instruction that performs "result = a0 op a1".
|
|
* This could be a MIPS instruction or a function call. (If the result
|
|
* comes back in a register other than a0, you can override "result".)
|
|
*
|
|
* If "chkzero" is set to 1, we perform a divide-by-zero check on
|
|
* vCC (a1). Useful for integer division and modulus. Note that we
|
|
* *don't* check for (INT_MIN / -1) here, because the CPU handles it
|
|
* correctly.
|
|
*
|
|
* For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
|
|
* xor-int, shl-int, shr-int, ushr-int
|
|
*/
|
|
/* binop vAA, vBB, vCC */
|
|
srl a4, rINST, 8 # a4 <- AA
|
|
lbu a2, 2(rPC) # a2 <- BB
|
|
lbu a3, 3(rPC) # a3 <- CC
|
|
GET_VREG a0, a2 # a0 <- vBB
|
|
GET_VREG a1, a3 # a1 <- vCC
|
|
.if $chkzero
|
|
beqz a1, common_errDivideByZero # is second operand zero?
|
|
.endif
|
|
FETCH_ADVANCE_INST 2 # advance rPC, load rINST
|
|
$preinstr # optional op
|
|
$instr # $result <- op, a0-a3 changed
|
|
GET_INST_OPCODE v0 # extract opcode from rINST
|
|
SET_VREG $result, a4 # vAA <- $result
|
|
GOTO_OPCODE v0 # jump to next instruction
|