32 lines
1.5 KiB
ArmAsm
32 lines
1.5 KiB
ArmAsm
%default {"preinstr":"", "result":"a0", "chkzero":"0"}
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/*
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* Generic 32-bit binary operation. Provide an "instr" line that
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* specifies an instruction that performs "result = a0 op a1".
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* This could be a MIPS instruction or a function call. (If the result
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* comes back in a register other than a0, you can override "result".)
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*
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* If "chkzero" is set to 1, we perform a divide-by-zero check on
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* vCC (a1). Useful for integer division and modulus. Note that we
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* *don't* check for (INT_MIN / -1) here, because the CPU handles it
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* correctly.
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*
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* For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
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* xor-int, shl-int, shr-int, ushr-int
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*/
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/* binop vAA, vBB, vCC */
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FETCH(a0, 1) # a0 <- CCBB
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GET_OPA(rOBJ) # rOBJ <- AA
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srl a3, a0, 8 # a3 <- CC
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and a2, a0, 255 # a2 <- BB
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GET_VREG(a1, a3) # a1 <- vCC
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GET_VREG(a0, a2) # a0 <- vBB
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.if $chkzero
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# is second operand zero?
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beqz a1, common_errDivideByZero
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.endif
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FETCH_ADVANCE_INST(2) # advance rPC, load rINST
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$preinstr # optional op
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$instr # $result <- op, a0-a3 changed
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GET_INST_OPCODE(t0) # extract opcode from rINST
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SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result
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