332 lines
10 KiB
ArmAsm
332 lines
10 KiB
ArmAsm
/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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Art assembly interpreter notes:
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First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't
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handle invoke, allows higher-level code to create frame & shadow frame.
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Once that's working, support direct entry code & eliminate shadow frame (and
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excess locals allocation.
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Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the
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base of the vreg array within the shadow frame. Access the other fields,
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dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue
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the shadow frame mechanism of double-storing object references - via xFP &
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number_of_vregs_.
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*/
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/*
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ARM64 Runtime register usage conventions.
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r0 : w0 is 32-bit return register and x0 is 64-bit.
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r0-r7 : Argument registers.
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r8-r15 : Caller save registers (used as temporary registers).
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r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by
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the linker, by the trampolines and other stubs (the backend uses
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these as temporary registers).
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r18 : Caller save register (used as temporary register).
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r19 : Pointer to thread-local storage.
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r20-r29: Callee save registers.
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r30 : (lr) is reserved (the link register).
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rsp : (sp) is reserved (the stack pointer).
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rzr : (zr) is reserved (the zero register).
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Floating-point registers
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v0-v31
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v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit).
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This is analogous to the C/C++ (hard-float) calling convention.
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v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions.
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Also used as temporary and codegen scratch registers.
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v0-v7 and v16-v31 : trashed across C calls.
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v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved).
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v16-v31: Used as codegen temp/scratch.
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v8-v15 : Can be used for promotion.
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Must maintain 16-byte stack alignment.
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Mterp notes:
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The following registers have fixed assignments:
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reg nick purpose
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x20 xPC interpreted program counter, used for fetching instructions
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x21 xFP interpreted frame pointer, used for accessing locals and args
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x22 xSELF self (Thread) pointer
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x23 xINST first 16-bit code unit of current instruction
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x24 xIBASE interpreted instruction base pointer, used for computed goto
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x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later).
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x26 wPROFILE jit profile hotness countdown
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x16 ip scratch reg
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x17 ip2 scratch reg (used by macros)
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Macros are provided for common operations. They MUST NOT alter unspecified registers or condition
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codes.
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*/
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/*
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* This is a #include, not a %include, because we want the C pre-processor
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* to expand the macros into assembler assignment statements.
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*/
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#include "asm_support.h"
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#define MTERP_PROFILE_BRANCHES 1
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#define MTERP_LOGGING 0
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/* During bringup, we'll use the shadow frame model instead of xFP */
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/* single-purpose registers, given names for clarity */
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#define xPC x20
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#define xFP x21
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#define xSELF x22
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#define xINST x23
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#define wINST w23
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#define xIBASE x24
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#define xREFS x25
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#define wPROFILE w26
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#define xPROFILE x26
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#define ip x16
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#define ip2 x17
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/*
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* Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So,
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* to access other shadow frame fields, we need to use a backwards offset. Define those here.
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*/
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#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
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#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
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#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
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#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
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#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
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#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
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#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
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#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
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#define OFF_FP_SHADOWFRAME OFF_FP(0)
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/*
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* "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must
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* be done *before* something throws.
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*
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* It's okay to do this more than once.
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*
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* NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
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* dex byte codes. However, the rest of the runtime expects dex pc to be an instruction
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* offset into the code_items_[] array. For effiency, we will "export" the
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* current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
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* to convert to a dex pc when needed.
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*/
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.macro EXPORT_PC
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str xPC, [xFP, #OFF_FP_DEX_PC_PTR]
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.endm
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/*
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* Fetch the next instruction from xPC into wINST. Does not advance xPC.
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*/
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.macro FETCH_INST
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ldrh wINST, [xPC]
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.endm
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/*
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* Fetch the next instruction from the specified offset. Advances xPC
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* to point to the next instruction. "_count" is in 16-bit code units.
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*
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* Because of the limited size of immediate constants on ARM, this is only
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* suitable for small forward movements (i.e. don't try to implement "goto"
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* with this).
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*
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* This must come AFTER anything that can throw an exception, or the
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* exception catch may miss. (This also implies that it must come after
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* EXPORT_PC.)
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*/
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.macro FETCH_ADVANCE_INST count
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ldrh wINST, [xPC, #((\count)*2)]!
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.endm
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/*
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* The operation performed here is similar to FETCH_ADVANCE_INST, except the
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* src and dest registers are parameterized (not hard-wired to xPC and xINST).
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*/
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.macro PREFETCH_ADVANCE_INST dreg, sreg, count
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ldrh \dreg, [\sreg, #((\count)*2)]!
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.endm
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/*
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* Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load
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* xINST ahead of possible exception point. Be sure to manually advance xPC
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* later.
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*/
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.macro PREFETCH_INST count
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ldrh wINST, [xPC, #((\count)*2)]
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.endm
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/* Advance xPC by some number of code units. */
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.macro ADVANCE count
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add xPC, xPC, #((\count)*2)
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.endm
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/*
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* Fetch the next instruction from an offset specified by _reg and advance xPC.
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* xPC to point to the next instruction. "_reg" must specify the distance
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* in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags.
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*
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*/
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.macro FETCH_ADVANCE_INST_RB reg
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add xPC, xPC, \reg, sxtw
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ldrh wINST, [xPC]
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.endm
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/*
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* Fetch a half-word code unit from an offset past the current PC. The
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* "_count" value is in 16-bit code units. Does not advance xPC.
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*
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* The "_S" variant works the same but treats the value as signed.
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*/
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.macro FETCH reg, count
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ldrh \reg, [xPC, #((\count)*2)]
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.endm
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.macro FETCH_S reg, count
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ldrsh \reg, [xPC, #((\count)*2)]
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.endm
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/*
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* Fetch one byte from an offset past the current PC. Pass in the same
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* "_count" as you would for FETCH, and an additional 0/1 indicating which
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* byte of the halfword you want (lo/hi).
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*/
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.macro FETCH_B reg, count, byte
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ldrb \reg, [xPC, #((\count)*2+(\byte))]
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.endm
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/*
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* Put the instruction's opcode field into the specified register.
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*/
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.macro GET_INST_OPCODE reg
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and \reg, xINST, #255
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.endm
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/*
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* Put the prefetched instruction's opcode field into the specified register.
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*/
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.macro GET_PREFETCHED_OPCODE oreg, ireg
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and \oreg, \ireg, #255
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.endm
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/*
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* Begin executing the opcode in _reg. Clobbers reg
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*/
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.macro GOTO_OPCODE reg
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add \reg, xIBASE, \reg, lsl #${handler_size_bits}
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br \reg
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.endm
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.macro GOTO_OPCODE_BASE base,reg
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add \reg, \base, \reg, lsl #${handler_size_bits}
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br \reg
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.endm
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/*
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* Get/set the 32-bit value from a Dalvik register.
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*/
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.macro GET_VREG reg, vreg
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ldr \reg, [xFP, \vreg, uxtw #2]
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.endm
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.macro SET_VREG reg, vreg
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str \reg, [xFP, \vreg, uxtw #2]
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str wzr, [xREFS, \vreg, uxtw #2]
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.endm
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.macro SET_VREG_OBJECT reg, vreg, tmpreg
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str \reg, [xFP, \vreg, uxtw #2]
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str \reg, [xREFS, \vreg, uxtw #2]
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.endm
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/*
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* Get/set the 64-bit value from a Dalvik register.
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* TUNING: can we do better here?
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*/
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.macro GET_VREG_WIDE reg, vreg
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add ip2, xFP, \vreg, lsl #2
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ldr \reg, [ip2]
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.endm
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.macro SET_VREG_WIDE reg, vreg
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add ip2, xFP, \vreg, lsl #2
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str \reg, [ip2]
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add ip2, xREFS, \vreg, lsl #2
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str xzr, [ip2]
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.endm
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/*
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* Get the 32-bit value from a Dalvik register and sign-extend to 64-bit.
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* Used to avoid an extra instruction in int-to-long.
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*/
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.macro GET_VREG_S reg, vreg
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ldrsw \reg, [xFP, \vreg, uxtw #2]
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.endm
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/*
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* Convert a virtual register index into an address.
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*/
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.macro VREG_INDEX_TO_ADDR reg, vreg
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add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */
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.endm
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/*
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* Refresh handler table.
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*/
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.macro REFRESH_IBASE
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ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET]
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.endm
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/*
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* Save two registers to the stack.
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*/
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.macro SAVE_TWO_REGS reg1, reg2, offset
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stp \reg1, \reg2, [sp, #(\offset)]
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.cfi_rel_offset \reg1, (\offset)
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.cfi_rel_offset \reg2, (\offset) + 8
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.endm
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/*
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* Restore two registers from the stack.
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*/
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.macro RESTORE_TWO_REGS reg1, reg2, offset
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ldp \reg1, \reg2, [sp, #(\offset)]
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.cfi_restore \reg1
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.cfi_restore \reg2
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.endm
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/*
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* Increase frame size and save two registers to the bottom of the stack.
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*/
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.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
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stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
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.cfi_adjust_cfa_offset (\frame_adjustment)
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.cfi_rel_offset \reg1, 0
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.cfi_rel_offset \reg2, 8
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.endm
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/*
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* Restore two registers from the bottom of the stack and decrease frame size.
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*/
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.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment
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ldp \reg1, \reg2, [sp], #(\frame_adjustment)
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.cfi_restore \reg1
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.cfi_restore \reg2
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.cfi_adjust_cfa_offset -(\frame_adjustment)
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.endm
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