34 lines
1.7 KiB
ArmAsm
34 lines
1.7 KiB
ArmAsm
%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"}
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/*
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* Generic 64-bit "/2addr" binary operation. Provide an "instr" line
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* that specifies an instruction that performs "result = r0-r1 op r2-r3".
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* This could be an ARM instruction or a function call. (If the result
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* comes back in a register other than r0, you can override "result".)
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*
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* If "chkzero" is set to 1, we perform a divide-by-zero check on
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* vCC (r1). Useful for integer division and modulus.
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*
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* For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
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* and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
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* sub-double/2addr, mul-double/2addr, div-double/2addr,
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* rem-double/2addr
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*/
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/* binop/2addr vA, vB */
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mov r1, rINST, lsr #12 @ r1<- B
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ubfx rINST, rINST, #8, #4 @ rINST<- A
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VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B]
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VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A]
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ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
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ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
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.if $chkzero
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orrs ip, r2, r3 @ second arg (r2-r3) is zero?
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beq common_errDivideByZero
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.endif
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CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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$preinstr @ optional op; may set condition codes
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$instr @ result<- op, r0-r3 changed
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GET_INST_OPCODE ip @ extract opcode from rINST
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stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1
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GOTO_OPCODE ip @ jump to next instruction
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/* 12-15 instructions */
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