38 lines
1.9 KiB
ArmAsm
38 lines
1.9 KiB
ArmAsm
%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"}
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/*
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* Generic 64-bit binary operation. Provide an "instr" line that
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* specifies an instruction that performs "result = r0-r1 op r2-r3".
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* This could be an ARM instruction or a function call. (If the result
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* comes back in a register other than r0, you can override "result".)
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*
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* If "chkzero" is set to 1, we perform a divide-by-zero check on
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* vCC (r1). Useful for integer division and modulus.
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*
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* for: add-long, sub-long, div-long, rem-long, and-long, or-long,
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* xor-long, add-double, sub-double, mul-double, div-double,
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* rem-double
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*
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* IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
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*/
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/* binop vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov rINST, rINST, lsr #8 @ rINST<- AA
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and r2, r0, #255 @ r2<- BB
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mov r3, r0, lsr #8 @ r3<- CC
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VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA]
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VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB]
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC]
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ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
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ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
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.if $chkzero
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orrs ip, r2, r3 @ second arg (r2-r3) is zero?
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beq common_errDivideByZero
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.endif
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CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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$preinstr @ optional op; may set condition codes
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$instr @ result<- op, r0-r3 changed
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GET_INST_OPCODE ip @ extract opcode from rINST
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stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1
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GOTO_OPCODE ip @ jump to next instruction
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/* 14-17 instructions */
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