32 lines
1.6 KiB
ArmAsm
32 lines
1.6 KiB
ArmAsm
%default {"preinstr":"", "result":"r0", "chkzero":"0"}
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/*
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* Generic 32-bit "/2addr" binary operation. Provide an "instr" line
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* that specifies an instruction that performs "result = r0 op r1".
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* This could be an ARM instruction or a function call. (If the result
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* comes back in a register other than r0, you can override "result".)
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*
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* If "chkzero" is set to 1, we perform a divide-by-zero check on
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* vCC (r1). Useful for integer division and modulus.
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*
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* For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
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* rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
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* shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
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* sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
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*/
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/* binop/2addr vA, vB */
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mov r3, rINST, lsr #12 @ r3<- B
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ubfx r9, rINST, #8, #4 @ r9<- A
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GET_VREG r1, r3 @ r1<- vB
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GET_VREG r0, r9 @ r0<- vA
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.if $chkzero
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cmp r1, #0 @ is second operand zero?
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beq common_errDivideByZero
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.endif
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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$preinstr @ optional op; may set condition codes
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$instr @ $result<- op, r0-r3 changed
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG $result, r9 @ vAA<- $result
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GOTO_OPCODE ip @ jump to next instruction
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/* 10-13 instructions */
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