upload android base code part8
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android/toolchain/binutils/binutils-2.25/opcodes/alpha-dis.c
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android/toolchain/binutils/binutils-2.25/opcodes/alpha-dis.c
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/* alpha-dis.c -- Disassemble Alpha AXP instructions
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Copyright (C) 1996-2014 Free Software Foundation, Inc.
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Contributed by Richard Henderson <rth@tamu.edu>,
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patterned after the PPC opcode handling written by Ian Lance Taylor.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "dis-asm.h"
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#include "opcode/alpha.h"
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/* OSF register names. */
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static const char * const osf_regnames[64] = {
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"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
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"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
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"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
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"t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
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"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
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"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
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};
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/* VMS register names. */
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static const char * const vms_regnames[64] = {
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"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
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"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
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"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
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"R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
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"F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
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"F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
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"F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
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"F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
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};
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/* Disassemble Alpha instructions. */
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int
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print_insn_alpha (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
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const char * const * regnames;
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const struct alpha_opcode *opcode, *opcode_end;
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const unsigned char *opindex;
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unsigned insn, op, isa_mask;
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int need_comma;
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/* Initialize the majorop table the first time through */
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if (!opcode_index[0])
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{
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opcode = alpha_opcodes;
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opcode_end = opcode + alpha_num_opcodes;
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for (op = 0; op < AXP_NOPS; ++op)
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{
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opcode_index[op] = opcode;
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while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
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++opcode;
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}
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opcode_index[op] = opcode;
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}
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if (info->flavour == bfd_target_evax_flavour)
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regnames = vms_regnames;
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else
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regnames = osf_regnames;
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isa_mask = AXP_OPCODE_NOPAL;
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switch (info->mach)
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{
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case bfd_mach_alpha_ev4:
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isa_mask |= AXP_OPCODE_EV4;
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break;
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case bfd_mach_alpha_ev5:
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isa_mask |= AXP_OPCODE_EV5;
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break;
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case bfd_mach_alpha_ev6:
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isa_mask |= AXP_OPCODE_EV6;
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break;
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}
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/* Read the insn into a host word */
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{
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bfd_byte buffer[4];
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int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getl32 (buffer);
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}
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/* Get the major opcode of the instruction. */
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op = AXP_OP (insn);
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/* Find the first match in the opcode table. */
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opcode_end = opcode_index[op + 1];
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for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
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{
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if ((insn ^ opcode->opcode) & opcode->mask)
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continue;
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if (!(opcode->flags & isa_mask))
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continue;
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/* Make two passes over the operands. First see if any of them
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have extraction functions, and, if they do, make sure the
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instruction is valid. */
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{
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int invalid = 0;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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const struct alpha_operand *operand = alpha_operands + *opindex;
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if (operand->extract)
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(*operand->extract) (insn, &invalid);
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}
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if (invalid)
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continue;
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}
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/* The instruction is valid. */
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goto found;
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}
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/* No instruction found */
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(*info->fprintf_func) (info->stream, ".long %#08x", insn);
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return 4;
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found:
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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if (opcode->operands[0] != 0)
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(*info->fprintf_func) (info->stream, "\t");
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/* Now extract and print the operands. */
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need_comma = 0;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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const struct alpha_operand *operand = alpha_operands + *opindex;
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int value;
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/* Operands that are marked FAKE are simply ignored. We
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already made sure that the extract function considered
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the instruction to be valid. */
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if ((operand->flags & AXP_OPERAND_FAKE) != 0)
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continue;
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/* Extract the value from the instruction. */
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if (operand->extract)
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value = (*operand->extract) (insn, (int *) NULL);
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else
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{
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value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
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if (operand->flags & AXP_OPERAND_SIGNED)
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{
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int signbit = 1 << (operand->bits - 1);
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value = (value ^ signbit) - signbit;
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}
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}
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if (need_comma &&
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((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
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!= AXP_OPERAND_PARENS))
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{
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(*info->fprintf_func) (info->stream, ",");
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}
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if (operand->flags & AXP_OPERAND_PARENS)
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(*info->fprintf_func) (info->stream, "(");
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/* Print the operand as directed by the flags. */
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if (operand->flags & AXP_OPERAND_IR)
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(*info->fprintf_func) (info->stream, "%s", regnames[value]);
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else if (operand->flags & AXP_OPERAND_FPR)
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(*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
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else if (operand->flags & AXP_OPERAND_RELATIVE)
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(*info->print_address_func) (memaddr + 4 + value, info);
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else if (operand->flags & AXP_OPERAND_SIGNED)
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(*info->fprintf_func) (info->stream, "%d", value);
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else
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(*info->fprintf_func) (info->stream, "%#x", value);
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if (operand->flags & AXP_OPERAND_PARENS)
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(*info->fprintf_func) (info->stream, ")");
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need_comma = 1;
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}
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return 4;
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}
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