upload android base code part6
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35396 changed files with 9188716 additions and 0 deletions
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/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __ARM_TRUSTZONE_H__
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#define __ARM_TRUSTZONE_H__
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#include <Uefi.h>
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// Setup TZ Protection Controller
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#define TZPC_DECPROT_0 0
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#define TZPC_DECPROT_1 1
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#define TZPC_DECPROT_2 2
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#define TZPC_DECPROT_MAX 2
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/**
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FIXME: Need documentation
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**/
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EFI_STATUS
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TZPCSetDecProtBits (
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IN UINTN TzpcBase,
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IN UINTN TzpcId,
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IN UINTN Bits
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);
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/**
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FIXME: Need documentation
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**/
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EFI_STATUS
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TZPCClearDecProtBits (
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IN UINTN TzpcBase,
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IN UINTN TzpcId,
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IN UINTN Bits
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);
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// Setup TZ Address Space Controller
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#define TZASC_REGION_ENABLED 1
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#define TZASC_REGION_DISABLED 0
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#define TZASC_REGION_SIZE_32KB 0xE
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#define TZASC_REGION_SIZE_64KB 0xF
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#define TZASC_REGION_SIZE_128KB 0x10
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#define TZASC_REGION_SIZE_256KB 0x11
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#define TZASC_REGION_SIZE_512KB 0x12
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#define TZASC_REGION_SIZE_1MB 0x13
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#define TZASC_REGION_SIZE_2MB 0x14
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#define TZASC_REGION_SIZE_4MB 0x15
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#define TZASC_REGION_SIZE_8MB 0x16
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#define TZASC_REGION_SIZE_16MB 0x17
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#define TZASC_REGION_SIZE_32MB 0x18
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#define TZASC_REGION_SIZE_64MB 0x19
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#define TZASC_REGION_SIZE_128MB 0x1A
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#define TZASC_REGION_SIZE_256MB 0x1B
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#define TZASC_REGION_SIZE_512MB 0x1C
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#define TZASC_REGION_SIZE_1GB 0x1D
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#define TZASC_REGION_SIZE_2GB 0x1E
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#define TZASC_REGION_SIZE_4GB 0x1F
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#define TZASC_REGION_SECURITY_SR (1 << 3)
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#define TZASC_REGION_SECURITY_SW (1 << 2)
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#define TZASC_REGION_SECURITY_SRW (TZASC_REGION_SECURITY_SR|TZASC_REGION_SECURITY_SW)
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#define TZASC_REGION_SECURITY_NSR (1 << 1)
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#define TZASC_REGION_SECURITY_NSW 1
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#define TZASC_REGION_SECURITY_NSRW (TZASC_REGION_SECURITY_NSR|TZASC_REGION_SECURITY_NSW)
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/**
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FIXME: Need documentation
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**/
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EFI_STATUS
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TZASCSetRegion (
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IN INTN TzascBase,
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IN UINTN RegionId,
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IN UINTN Enabled,
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IN UINTN LowAddress,
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IN UINTN HighAddress,
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IN UINTN Size,
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IN UINTN Security
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);
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#endif
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/** @file HDLcd.h
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _HDLCD_H_
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#define _HDLCD_H_
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//
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// HDLCD Controller Register Offsets
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//
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#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
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#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
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#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
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#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
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#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
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#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
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#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
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#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
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#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
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#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
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#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
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#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
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#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
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#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
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#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
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#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
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#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
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#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
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#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
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#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
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#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
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#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
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#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
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#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
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//
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// HDLCD Values of registers
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//
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// HDLCD Interrupt mask, clear and status register
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#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
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#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
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#define HDLCD_SYNC BIT2 /* Vertical sync */
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#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
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// CLCD_CONTROL Control register
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#define HDLCD_DISABLE 0
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#define HDLCD_ENABLE BIT0
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// Bus Options
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#define HDLCD_BURST_1 BIT0
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#define HDLCD_BURST_2 BIT1
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#define HDLCD_BURST_4 BIT2
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#define HDLCD_BURST_8 BIT3
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#define HDLCD_BURST_16 BIT4
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// Polarities - HIGH
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#define HDLCD_VSYNC_HIGH BIT0
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#define HDLCD_HSYNC_HIGH BIT1
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#define HDLCD_DATEN_HIGH BIT2
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#define HDLCD_DATA_HIGH BIT3
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#define HDLCD_PXCLK_HIGH BIT4
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// Polarities - LOW (for completion and for ease of understanding the hardware settings)
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#define HDLCD_VSYNC_LOW 0
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#define HDLCD_HSYNC_LOW 0
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#define HDLCD_DATEN_LOW 0
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#define HDLCD_DATA_LOW 0
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#define HDLCD_PXCLK_LOW 0
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// Pixel Format
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#define HDLCD_LITTLE_ENDIAN (0 << 31)
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#define HDLCD_BIG_ENDIAN (1 << 31)
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// Number of bytes per pixel
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#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
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#endif /* _HDLCD_H_ */
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@ -0,0 +1,231 @@
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/** @file
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __PL011_UART_H__
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#define __PL011_UART_H__
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#include <Uefi.h>
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#include <Protocol/SerialIo.h>
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// PL011 Registers
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTMIS 0x040
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#define UARTICR 0x044
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#define UARTDMACR 0x048
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#define UARTPID0 0xFE0
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#define UARTPID1 0xFE4
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#define UARTPID2 0xFE8
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#define UARTPID3 0xFEC
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// Data status bits
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#define UART_DATA_ERROR_MASK 0x0F00
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// Status reg bits
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#define UART_STATUS_ERROR_MASK 0x0F
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// Flag reg bits
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#define PL011_UARTFR_RI (1 << 8) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 3) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 1) // Data set ready
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#define PL011_UARTFR_CTS (1 << 0) // Clear to send
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// Flag reg bits - alternative names
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#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
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#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
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#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
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#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
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#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
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// Control reg bits
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#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
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#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
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#define PL011_UARTCR_RTS (1 << 11) // Request to send
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#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
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#define PL011_UARTCR_RXE (1 << 9) // Receive enable
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#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
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#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
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#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
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// Line Control Register Bits
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#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
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#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
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#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
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#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
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#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
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#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
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#define PL011_VER_R1P4 0x2
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/*
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Programmed hardware of Serial port.
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@return Always return EFI_UNSUPPORTED.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartInitializePort (
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IN OUT UINTN UartBase,
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IN OUT UINT64 *BaudRate,
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IN OUT UINT32 *ReceiveFifoDepth,
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IN OUT EFI_PARITY_TYPE *Parity,
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IN OUT UINT8 *DataBits,
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IN OUT EFI_STOP_BITS_TYPE *StopBits
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);
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/**
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Assert or deassert the control signals on a serial port.
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The following control signals are set according their bit settings :
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. Request to Send
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. Data Terminal Ready
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@param[in] UartBase UART registers base address
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@param[in] Control The following bits are taken into account :
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. EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
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"Request To Send" control signal if this bit is
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equal to one/zero.
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. EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
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the "Data Terminal Ready" control signal if this
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bit is equal to one/zero.
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. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
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the hardware loopback if this bit is equal to
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one/zero.
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. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
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. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
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disable the hardware flow control based on CTS (Clear
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To Send) and RTS (Ready To Send) control signals.
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@retval RETURN_SUCCESS The new control bits were set on the serial device.
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@retval RETURN_UNSUPPORTED The serial device does not support this operation.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartSetControl (
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IN UINTN UartBase,
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IN UINT32 Control
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);
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/**
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Retrieve the status of the control bits on a serial device.
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@param[in] UartBase UART registers base address
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@param[out] Control Status of the control bits on a serial device :
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. EFI_SERIAL_DATA_CLEAR_TO_SEND, EFI_SERIAL_DATA_SET_READY,
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EFI_SERIAL_RING_INDICATE, EFI_SERIAL_CARRIER_DETECT,
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EFI_SERIAL_REQUEST_TO_SEND, EFI_SERIAL_DATA_TERMINAL_READY
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are all related to the DTE (Data Terminal Equipment) and
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DCE (Data Communication Equipment) modes of operation of
|
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the serial device.
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. EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the receive
|
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buffer is empty, 0 otherwise.
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. EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the transmit
|
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buffer is empty, 0 otherwise.
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. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if the
|
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hardware loopback is enabled (the ouput feeds the receive
|
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buffer), 0 otherwise.
|
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. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if a
|
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loopback is accomplished by software, 0 otherwise.
|
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. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to one if the
|
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hardware flow control based on CTS (Clear To Send) and RTS
|
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(Ready To Send) control signals is enabled, 0 otherwise.
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||||
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@retval RETURN_SUCCESS The control bits were read from the serial device.
|
||||
|
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartGetControl (
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IN UINTN UartBase,
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OUT UINT32 *Control
|
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);
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/**
|
||||
Write data to serial device.
|
||||
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@param Buffer Point of data buffer which need to be written.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Write data failed.
|
||||
@retval !0 Actual number of bytes written to serial device.
|
||||
|
||||
**/
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UINTN
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EFIAPI
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PL011UartWrite (
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IN UINTN UartBase,
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IN UINT8 *Buffer,
|
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IN UINTN NumberOfBytes
|
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);
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/**
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Read data from serial device and save the data in buffer.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Read data failed.
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@retval !0 Actual number of bytes read from serial device.
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**/
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UINTN
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EFIAPI
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PL011UartRead (
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IN UINTN UartBase,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes
|
||||
);
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||||
/**
|
||||
Check to see if any data is available to be read from the debug device.
|
||||
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||||
@retval EFI_SUCCESS At least one byte of data is available to be read
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||||
@retval EFI_NOT_READY No data is available to be read
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
|
||||
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||||
**/
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BOOLEAN
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EFIAPI
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PL011UartPoll (
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IN UINTN UartBase
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||||
);
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#endif
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|
|
@ -0,0 +1,56 @@
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/** @file
|
||||
*
|
||||
* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
|
||||
#ifndef __PL031_REAL_TIME_CLOCK_H__
|
||||
#define __PL031_REAL_TIME_CLOCK_H__
|
||||
|
||||
// PL031 Registers
|
||||
#define PL031_RTC_DR_DATA_REGISTER 0x000
|
||||
#define PL031_RTC_MR_MATCH_REGISTER 0x004
|
||||
#define PL031_RTC_LR_LOAD_REGISTER 0x008
|
||||
#define PL031_RTC_CR_CONTROL_REGISTER 0x00C
|
||||
#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010
|
||||
#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014
|
||||
#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018
|
||||
#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C
|
||||
#define PL031_RTC_PERIPH_ID0 0xFE0
|
||||
#define PL031_RTC_PERIPH_ID1 0xFE4
|
||||
#define PL031_RTC_PERIPH_ID2 0xFE8
|
||||
#define PL031_RTC_PERIPH_ID3 0xFEC
|
||||
#define PL031_RTC_PCELL_ID0 0xFF0
|
||||
#define PL031_RTC_PCELL_ID1 0xFF4
|
||||
#define PL031_RTC_PCELL_ID2 0xFF8
|
||||
#define PL031_RTC_PCELL_ID3 0xFFC
|
||||
|
||||
// PL031 Values
|
||||
#define PL031_RTC_ENABLED 0x00000001
|
||||
#define PL031_SET_IRQ_MASK 0x00000001
|
||||
#define PL031_IRQ_TRIGGERED 0x00000001
|
||||
#define PL031_CLEAR_IRQ 0x00000001
|
||||
|
||||
#define PL031_COUNTS_PER_SECOND 1
|
||||
|
||||
// Define EPOCH (1970-JANUARY-01) in the Julian Date representation
|
||||
#define EPOCH_JULIAN_DATE 2440588
|
||||
|
||||
// Seconds per unit
|
||||
#define SEC_PER_MIN ((UINTN) 60)
|
||||
#define SEC_PER_HOUR ((UINTN) 3600)
|
||||
#define SEC_PER_DAY ((UINTN) 86400)
|
||||
|
||||
#define SEC_PER_MONTH ((UINTN) 2,592,000)
|
||||
#define SEC_PER_YEAR ((UINTN) 31,536,000)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
|
||||
#ifndef __PL061_GPIO_H__
|
||||
#define __PL061_GPIO_H__
|
||||
|
||||
#include <Protocol/EmbeddedGpio.h>
|
||||
|
||||
// PL061 GPIO Registers
|
||||
#define PL061_GPIO_DATA_REG 0x000
|
||||
#define PL061_GPIO_DIR_REG 0x400
|
||||
#define PL061_GPIO_IS_REG 0x404
|
||||
#define PL061_GPIO_IBE_REG 0x408
|
||||
#define PL061_GPIO_IEV_REG 0x40C
|
||||
#define PL061_GPIO_IE_REG 0x410
|
||||
#define PL061_GPIO_RIS_REG 0x414
|
||||
#define PL061_GPIO_MIS_REG 0x410
|
||||
#define PL061_GPIO_IC_REG 0x41C
|
||||
#define PL061_GPIO_AFSEL_REG 0x420
|
||||
|
||||
#define PL061_GPIO_PERIPH_ID0 0xFE0
|
||||
#define PL061_GPIO_PERIPH_ID1 0xFE4
|
||||
#define PL061_GPIO_PERIPH_ID2 0xFE8
|
||||
#define PL061_GPIO_PERIPH_ID3 0xFEC
|
||||
|
||||
#define PL061_GPIO_PCELL_ID0 0xFF0
|
||||
#define PL061_GPIO_PCELL_ID1 0xFF4
|
||||
#define PL061_GPIO_PCELL_ID2 0xFF8
|
||||
#define PL061_GPIO_PCELL_ID3 0xFFC
|
||||
|
||||
|
||||
#define PL061_GPIO_PINS 8
|
||||
|
||||
// All bits low except one bit high, native bit length
|
||||
#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
|
||||
|
||||
#endif // __PL061_GPIO_H__
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/** @file PL111Lcd.h
|
||||
|
||||
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _PL111LCD_H__
|
||||
#define _PL111LCD_H__
|
||||
|
||||
/**********************************************************************
|
||||
*
|
||||
* This header file contains all the bits of the PL111 that are
|
||||
* platform independent.
|
||||
*
|
||||
**********************************************************************/
|
||||
|
||||
// Controller Register Offsets
|
||||
#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
|
||||
#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
|
||||
#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
|
||||
#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
|
||||
#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
|
||||
#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
|
||||
#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
|
||||
#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
|
||||
#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
|
||||
#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
|
||||
#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
|
||||
#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
|
||||
#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
|
||||
#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
|
||||
|
||||
// Identification Register Offsets
|
||||
#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
|
||||
#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
|
||||
#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
|
||||
#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
|
||||
#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
|
||||
#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
|
||||
#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
|
||||
#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
|
||||
|
||||
#define PL111_CLCD_PERIPH_ID_0 0x11
|
||||
#define PL111_CLCD_PERIPH_ID_1 0x11
|
||||
#define PL111_CLCD_PERIPH_ID_2 0x04
|
||||
#define PL111_CLCD_PERIPH_ID_3 0x00
|
||||
#define PL111_CLCD_P_CELL_ID_0 0x0D
|
||||
#define PL111_CLCD_P_CELL_ID_1 0xF0
|
||||
#define PL111_CLCD_P_CELL_ID_2 0x05
|
||||
#define PL111_CLCD_P_CELL_ID_3 0xB1
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
// Register components (register bits)
|
||||
|
||||
// This should make life easier to program specific settings in the different registers
|
||||
// by simplifying the setting up of the individual bits of each register
|
||||
// and then assembling the final register value.
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_0
|
||||
#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_1
|
||||
#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_2
|
||||
#define PL111_BIT_SHIFT_PCD_HI 27
|
||||
#define PL111_BIT_SHIFT_BCD 26
|
||||
#define PL111_BIT_SHIFT_CPL 16
|
||||
#define PL111_BIT_SHIFT_IOE 14
|
||||
#define PL111_BIT_SHIFT_IPC 13
|
||||
#define PL111_BIT_SHIFT_IHS 12
|
||||
#define PL111_BIT_SHIFT_IVS 11
|
||||
#define PL111_BIT_SHIFT_ACB 6
|
||||
#define PL111_BIT_SHIFT_CLKSEL 5
|
||||
#define PL111_BIT_SHIFT_PCD_LO 0
|
||||
|
||||
#define PL111_BCD (1 << 26)
|
||||
#define PL111_IPC (1 << 13)
|
||||
#define PL111_IHS (1 << 12)
|
||||
#define PL111_IVS (1 << 11)
|
||||
|
||||
#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_3
|
||||
#define PL111_BIT_SHIFT_LEE 16
|
||||
#define PL111_BIT_SHIFT_LED 0
|
||||
|
||||
#define PL111_CTRL_WATERMARK (1 << 16)
|
||||
#define PL111_CTRL_LCD_V_COMP (1 << 12)
|
||||
#define PL111_CTRL_LCD_PWR (1 << 11)
|
||||
#define PL111_CTRL_BEPO (1 << 10)
|
||||
#define PL111_CTRL_BEBO (1 << 9)
|
||||
#define PL111_CTRL_BGR (1 << 8)
|
||||
#define PL111_CTRL_LCD_DUAL (1 << 7)
|
||||
#define PL111_CTRL_LCD_MONO_8 (1 << 6)
|
||||
#define PL111_CTRL_LCD_TFT (1 << 5)
|
||||
#define PL111_CTRL_LCD_BW (1 << 4)
|
||||
#define PL111_CTRL_LCD_1BPP (0 << 1)
|
||||
#define PL111_CTRL_LCD_2BPP (1 << 1)
|
||||
#define PL111_CTRL_LCD_4BPP (2 << 1)
|
||||
#define PL111_CTRL_LCD_8BPP (3 << 1)
|
||||
#define PL111_CTRL_LCD_16BPP (4 << 1)
|
||||
#define PL111_CTRL_LCD_24BPP (5 << 1)
|
||||
#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
|
||||
#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
|
||||
#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
|
||||
#define PL111_CTRL_LCD_EN 1
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_0
|
||||
#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
|
||||
#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
|
||||
#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
|
||||
#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_1
|
||||
#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
|
||||
#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
|
||||
#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
|
||||
#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_2
|
||||
#define PL111_BIT_MASK_PCD_HI 0xF8000000
|
||||
#define PL111_BIT_MASK_BCD 0x04000000
|
||||
#define PL111_BIT_MASK_CPL 0x03FF0000
|
||||
#define PL111_BIT_MASK_IOE 0x00004000
|
||||
#define PL111_BIT_MASK_IPC 0x00002000
|
||||
#define PL111_BIT_MASK_IHS 0x00001000
|
||||
#define PL111_BIT_MASK_IVS 0x00000800
|
||||
#define PL111_BIT_MASK_ACB 0x000007C0
|
||||
#define PL111_BIT_MASK_CLKSEL 0x00000020
|
||||
#define PL111_BIT_MASK_PCD_LO 0x0000001F
|
||||
|
||||
// Register: PL111_REG_LCD_TIMING_3
|
||||
#define PL111_BIT_MASK_LEE 0x00010000
|
||||
#define PL111_BIT_MASK_LED 0x0000007F
|
||||
|
||||
#endif /* _PL111LCD_H__ */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef PL301AXI_H_
|
||||
#define PL301AXI_H_
|
||||
|
||||
VOID PL301AxiInit(UINTN FAxiBase);
|
||||
|
||||
|
||||
#endif /* PL301AXI_H_ */
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef L2CACHELIB_H_
|
||||
#define L2CACHELIB_H_
|
||||
|
||||
#define L2X0_CACHEID 0x000
|
||||
#define L2X0_CTRL 0x100
|
||||
#define L2X0_AUXCTRL 0x104
|
||||
#define L230_TAG_LATENCY 0x108
|
||||
#define L230_DATA_LATENCY 0x10C
|
||||
#define L2X0_INTCLEAR 0x220
|
||||
#define L2X0_CACHE_SYNC 0x730
|
||||
#define L2X0_INVWAY 0x77C
|
||||
#define L2X0_CLEAN_WAY 0x7BC
|
||||
#define L2X0_PFCTRL 0xF60
|
||||
#define L2X0_PWRCTRL 0xF80
|
||||
|
||||
#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41
|
||||
#define L2X0_CACHEID_PARTNUM_PL310 0x03
|
||||
|
||||
#define L2X0_CTRL_ENABLED 0x1
|
||||
#define L2X0_CTRL_DISABLED 0x0
|
||||
|
||||
#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)
|
||||
#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)
|
||||
#define L2X0_AUXCTRL_EM (1 << 20)
|
||||
#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)
|
||||
#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)
|
||||
#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)
|
||||
#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)
|
||||
#define L2X0_AUXCTRL_SBO (1 << 25)
|
||||
#define L2X0_AUXCTRL_NSAC (1 << 27)
|
||||
#define L2x0_AUXCTRL_DPREFETCH (1 << 28)
|
||||
#define L2x0_AUXCTRL_IPREFETCH (1 << 29)
|
||||
#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)
|
||||
|
||||
#define L2x0_LATENCY_1_CYCLE 0
|
||||
#define L2x0_LATENCY_2_CYCLES 1
|
||||
#define L2x0_LATENCY_3_CYCLES 2
|
||||
#define L2x0_LATENCY_4_CYCLES 3
|
||||
#define L2x0_LATENCY_5_CYCLES 4
|
||||
#define L2x0_LATENCY_6_CYCLES 5
|
||||
#define L2x0_LATENCY_7_CYCLES 6
|
||||
#define L2x0_LATENCY_8_CYCLES 7
|
||||
|
||||
#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))
|
||||
#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
|
||||
#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
|
||||
|
||||
VOID
|
||||
L2x0CacheInit (
|
||||
IN UINTN L2x0Base,
|
||||
IN UINT32 L2x0TagLatencies,
|
||||
IN UINT32 L2x0DataLatencies,
|
||||
IN UINT32 L2x0AuxValue,
|
||||
IN UINT32 L2x0AuxMask,
|
||||
IN BOOLEAN CacheEnabled
|
||||
);
|
||||
|
||||
#endif /* L2CACHELIB_H_ */
|
||||
|
|
@ -0,0 +1,336 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _PL341DMC_H_
|
||||
#define _PL341DMC_H_
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINTN HasQos; // has QoS registers
|
||||
UINTN MaxChip; // number of memory chips accessible
|
||||
BOOLEAN IsUserCfg;
|
||||
UINT32 User0Cfg;
|
||||
UINT32 User2Cfg;
|
||||
UINT32 RefreshPeriod;
|
||||
UINT32 CasLatency;
|
||||
UINT32 WriteLatency;
|
||||
UINT32 t_mrd;
|
||||
UINT32 t_ras;
|
||||
UINT32 t_rc;
|
||||
UINT32 t_rcd;
|
||||
UINT32 t_rfc;
|
||||
UINT32 t_rp;
|
||||
UINT32 t_rrd;
|
||||
UINT32 t_wr;
|
||||
UINT32 t_wtr;
|
||||
UINT32 t_xp;
|
||||
UINT32 t_xsr;
|
||||
UINT32 t_esr;
|
||||
UINT32 MemoryCfg;
|
||||
UINT32 MemoryCfg2;
|
||||
UINT32 MemoryCfg3;
|
||||
UINT32 ChipCfg0;
|
||||
UINT32 ChipCfg1;
|
||||
UINT32 ChipCfg2;
|
||||
UINT32 ChipCfg3;
|
||||
UINT32 t_faw;
|
||||
UINT32 t_data_en;
|
||||
UINT32 t_wdata_en;
|
||||
UINT32 ModeReg;
|
||||
UINT32 ExtModeReg;
|
||||
} PL341_DMC_CONFIG;
|
||||
|
||||
/* Memory config bit fields */
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
|
||||
#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
|
||||
|
||||
#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
|
||||
#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
|
||||
#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
|
||||
#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
|
||||
|
||||
//
|
||||
// DMC Configuration Register Map
|
||||
//
|
||||
#define DMC_STATUS_REG 0x00
|
||||
#define DMC_COMMAND_REG 0x04
|
||||
#define DMC_DIRECT_CMD_REG 0x08
|
||||
#define DMC_MEMORY_CONFIG_REG 0x0C
|
||||
#define DMC_REFRESH_PRD_REG 0x10
|
||||
#define DMC_CAS_LATENCY_REG 0x14
|
||||
#define DMC_WRITE_LATENCY_REG 0x18
|
||||
#define DMC_T_MRD_REG 0x1C
|
||||
#define DMC_T_RAS_REG 0x20
|
||||
#define DMC_T_RC_REG 0x24
|
||||
#define DMC_T_RCD_REG 0x28
|
||||
#define DMC_T_RFC_REG 0x2C
|
||||
#define DMC_T_RP_REG 0x30
|
||||
#define DMC_T_RRD_REG 0x34
|
||||
#define DMC_T_WR_REG 0x38
|
||||
#define DMC_T_WTR_REG 0x3C
|
||||
#define DMC_T_XP_REG 0x40
|
||||
#define DMC_T_XSR_REG 0x44
|
||||
#define DMC_T_ESR_REG 0x48
|
||||
#define DMC_MEMORY_CFG2_REG 0x4C
|
||||
#define DMC_MEMORY_CFG3_REG 0x50
|
||||
#define DMC_T_FAW_REG 0x54
|
||||
#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
|
||||
#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
|
||||
|
||||
// Returns the state of the memory controller:
|
||||
#define DMC_STATUS_CONFIG 0x0
|
||||
#define DMC_STATUS_READY 0x1
|
||||
#define DMC_STATUS_PAUSED 0x2
|
||||
#define DMC_STATUS_LOWPOWER 0x3
|
||||
|
||||
// Changes the state of the memory controller:
|
||||
#define DMC_COMMAND_GO 0x0
|
||||
#define DMC_COMMAND_SLEEP 0x1
|
||||
#define DMC_COMMAND_WAKEUP 0x2
|
||||
#define DMC_COMMAND_PAUSE 0x3
|
||||
#define DMC_COMMAND_CONFIGURE 0x4
|
||||
#define DMC_COMMAND_ACTIVEPAUSE 0x7
|
||||
|
||||
// Determines the command required
|
||||
#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
|
||||
#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
|
||||
#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
|
||||
#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
|
||||
|
||||
|
||||
//
|
||||
// AXI ID configuration register map
|
||||
//
|
||||
#define DMC_ID_0_CFG_REG 0x100
|
||||
#define DMC_ID_1_CFG_REG 0x104
|
||||
#define DMC_ID_2_CFG_REG 0x108
|
||||
#define DMC_ID_3_CFG_REG 0x10C
|
||||
#define DMC_ID_4_CFG_REG 0x110
|
||||
#define DMC_ID_5_CFG_REG 0x114
|
||||
#define DMC_ID_6_CFG_REG 0x118
|
||||
#define DMC_ID_7_CFG_REG 0x11C
|
||||
#define DMC_ID_8_CFG_REG 0x120
|
||||
#define DMC_ID_9_CFG_REG 0x124
|
||||
#define DMC_ID_10_CFG_REG 0x128
|
||||
#define DMC_ID_11_CFG_REG 0x12C
|
||||
#define DMC_ID_12_CFG_REG 0x130
|
||||
#define DMC_ID_13_CFG_REG 0x134
|
||||
#define DMC_ID_14_CFG_REG 0x138
|
||||
#define DMC_ID_15_CFG_REG 0x13C
|
||||
|
||||
// Set the QoS
|
||||
#define DMC_ID_CFG_QOS_DISABLE 0
|
||||
#define DMC_ID_CFG_QOS_ENABLE 1
|
||||
#define DMC_ID_CFG_QOS_MIN 2
|
||||
|
||||
|
||||
//
|
||||
// Chip configuration register map
|
||||
//
|
||||
#define DMC_CHIP_0_CFG_REG 0x200
|
||||
#define DMC_CHIP_1_CFG_REG 0x204
|
||||
#define DMC_CHIP_2_CFG_REG 0x208
|
||||
#define DMC_CHIP_3_CFG_REG 0x20C
|
||||
|
||||
//
|
||||
// User Defined Pins
|
||||
//
|
||||
#define DMC_USER_STATUS_REG 0x300
|
||||
#define DMC_USER_0_CFG_REG 0x304
|
||||
#define DMC_USER_1_CFG_REG 0x308
|
||||
#define DMC_FEATURE_CRTL_REG 0x30C
|
||||
#define DMC_USER_2_CFG_REG 0x310
|
||||
|
||||
|
||||
//
|
||||
// PHY Register Settings
|
||||
//
|
||||
#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
|
||||
#define PHY_PTM_IOTERM 0xE04
|
||||
#define PHY_PTM_PLL_EN 0xe0c
|
||||
#define PHY_PTM_PLL_RANGE 0xe18
|
||||
#define PHY_PTM_FEEBACK_DIV 0xe1c
|
||||
#define PHY_PTM_RCLK_DIV 0xe20
|
||||
#define PHY_PTM_LOCK_STATUS 0xe28
|
||||
#define PHY_PTM_INIT_DONE 0xe34
|
||||
#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
|
||||
#define PHY_PTM_SQU_TRAINING 0xee8
|
||||
#define PHY_PTM_SQU_STAT 0xeec
|
||||
|
||||
// ==============================================================================
|
||||
// PIPD 40G DDR2/DDR3 PHY Register definitions
|
||||
//
|
||||
// Offsets from APB Base Address
|
||||
// ==============================================================================
|
||||
#define PHY_BYTE0_OFFSET 0x000
|
||||
#define PHY_BYTE1_OFFSET 0x200
|
||||
#define PHY_BYTE2_OFFSET 0x400
|
||||
#define PHY_BYTE3_OFFSET 0x600
|
||||
|
||||
#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
|
||||
|
||||
#define PHY_BYTE0_IOSTR_OFFSET 0x004
|
||||
#define PHY_BYTE1_IOSTR_OFFSET 0x204
|
||||
#define PHY_BYTE2_IOSTR_OFFSET 0x404
|
||||
#define PHY_BYTE3_IOSTR_OFFSET 0x604
|
||||
|
||||
|
||||
;//--------------------------------------------------------------------------
|
||||
|
||||
// DFI Clock ranges:
|
||||
|
||||
#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
|
||||
#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
|
||||
#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
|
||||
#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
|
||||
#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
|
||||
#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
|
||||
#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
|
||||
|
||||
|
||||
|
||||
#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
|
||||
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
// PLL Range
|
||||
|
||||
#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
|
||||
#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
|
||||
#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
|
||||
#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
|
||||
#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
|
||||
#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
|
||||
|
||||
#define TC_UIOLHNC_MASK 0x000003C0
|
||||
#define TC_UIOLHNC_SHIFT 0x6
|
||||
#define TC_UIOLHPC_MASK 0x0000003F
|
||||
#define TC_UIOLHPC_SHIFT 0x2
|
||||
#define TC_UIOHOCT_MASK 0x2
|
||||
#define TC_UIOHOCT_SHIFT 0x1
|
||||
#define TC_UIOHSTOP_SHIFT 0x0
|
||||
#define TC_UIOLHXC_VALUE 0x4
|
||||
|
||||
#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
|
||||
#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
|
||||
|
||||
|
||||
//--------------------------------------
|
||||
// JEDEC DDR2 Device Register definitions and settings
|
||||
//--------------------------------------
|
||||
#define DDR_MODESET_SHFT 14
|
||||
#define DDR_MODESET_MR 0x0 ;// Mode register
|
||||
#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
|
||||
#define DDR_MODESET_EMR2 0x2
|
||||
#define DDR_MODESET_EMR3 0x3
|
||||
|
||||
//
|
||||
// Extended Mode Register settings
|
||||
//
|
||||
#define DDR_EMR_OCD_MASK 0x0000380
|
||||
#define DDR_EMR_OCD_SHIFT 0x7
|
||||
#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
|
||||
#define DDR_EMR_RTT_SHIFT 0x2
|
||||
#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
|
||||
#define DDR_EMR_ODS_SHIFT 0x0001
|
||||
|
||||
// Termination Values:
|
||||
#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination
|
||||
#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
|
||||
#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
|
||||
|
||||
// Output Drive Strength Values:
|
||||
#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
|
||||
#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
|
||||
|
||||
// OCD values
|
||||
#define DDR_EMR_OCD_DEFAULT 0x7
|
||||
#define DDR_EMR_OCD_NS 0x0
|
||||
|
||||
#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
|
||||
|
||||
#define DDR_SDRAM_START_ADDR 0x10000000
|
||||
|
||||
|
||||
// ----------------------------------------
|
||||
// PHY IOTERM values
|
||||
// ----------------------------------------
|
||||
#define PHY_PTM_IOTERM_OFF 0x0
|
||||
#define PHY_PTM_IOTERM_150R 0x1
|
||||
#define PHY_PTM_IOTERM_75R 0x2
|
||||
#define PHY_PTM_IOTERM_50R 0x3
|
||||
|
||||
#define PHY_BYTE_IOSTR_60OHM 0x0
|
||||
#define PHY_BYTE_IOSTR_40OHM 0x1
|
||||
#define PHY_BYTE_IOSTR_30OHM 0x2
|
||||
#define PHY_BYTE_IOSTR_30AOHM 0x3
|
||||
|
||||
#define DDR2_MR_BURST_LENGTH_4 (2)
|
||||
#define DDR2_MR_BURST_LENGTH_8 (3)
|
||||
#define DDR2_MR_DLL_RESET (1 << 8)
|
||||
#define DDR2_MR_CAS_LATENCY_4 (4 << 4)
|
||||
#define DDR2_MR_CAS_LATENCY_5 (5 << 4)
|
||||
#define DDR2_MR_CAS_LATENCY_6 (6 << 4)
|
||||
#define DDR2_MR_WR_CYCLES_2 (1 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_3 (2 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_4 (3 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_5 (4 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_6 (5 << 9)
|
||||
|
||||
|
||||
VOID
|
||||
PL341DmcInit (
|
||||
IN UINTN DmcBase,
|
||||
IN PL341_DMC_CONFIG* DmcConfig
|
||||
);
|
||||
|
||||
VOID PL341DmcPhyInit (
|
||||
IN UINTN DmcPhyBase
|
||||
);
|
||||
|
||||
VOID PL341DmcTrainPHY (
|
||||
IN UINTN DmcPhyBase
|
||||
);
|
||||
|
||||
#endif /* _PL341DMC_H_ */
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef PL35xSMC_H_
|
||||
#define PL35xSMC_H_
|
||||
|
||||
#define PL350_SMC_DIRECT_CMD_OFFSET 0x10
|
||||
#define PL350_SMC_SET_CYCLES_OFFSET 0x14
|
||||
#define PL350_SMC_SET_OPMODE_OFFSET 0x18
|
||||
#define PL350_SMC_REFRESH_0_OFFSET 0x20
|
||||
#define PL350_SMC_REFRESH_1_OFFSET 0x24
|
||||
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))
|
||||
#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)
|
||||
|
||||
#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
|
||||
#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
|
||||
#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
|
||||
#define PL350_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
|
||||
#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
|
||||
#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
|
||||
#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
|
||||
#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
|
||||
#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
|
||||
#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
|
||||
#define PL350_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
|
||||
#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
|
||||
#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
|
||||
#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
|
||||
#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
|
||||
#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
|
||||
#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
|
||||
#define PL350_SMC_SET_OPMODE_SET_BAA (1 << 10)
|
||||
#define PL350_SMC_SET_OPMODE_SET_ADV (1 << 11)
|
||||
#define PL350_SMC_SET_OPMODE_SET_BLS (1 << 12)
|
||||
#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
|
||||
#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
|
||||
#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
|
||||
#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
|
||||
#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
|
||||
|
||||
#define PL350_SMC_SET_CYCLE_NAND_T_RC(t) (((t) & 0xF) << 0)
|
||||
#define PL350_SMC_SET_CYCLE_NAND_T_WC(t) (((t) & 0xF) << 4)
|
||||
#define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)
|
||||
#define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)
|
||||
#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)
|
||||
#define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)
|
||||
#define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)
|
||||
|
||||
#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t) (((t) & 0xF) << 0)
|
||||
#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t) (((t) & 0xF) << 4)
|
||||
#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)
|
||||
#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)
|
||||
#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)
|
||||
#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)
|
||||
#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME (1 << 20)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
|
||||
#ifndef _SP804_TIMER_H__
|
||||
#define _SP804_TIMER_H__
|
||||
|
||||
// SP804 Timer constants
|
||||
// Note: The SP804 Timer module comprises two timers, Timer_0 and Timer_1
|
||||
// These timers are identical and all their registers have an offset of 0x20
|
||||
// i.e. SP804_TIMER_0_LOAD_REG = 0x00 and SP804_TIMER_1_LOAD_REG = 0x20
|
||||
// Therefore, define all registers only once and adjust the base addresses by 0x20
|
||||
#define SP804_TIMER_LOAD_REG 0x00
|
||||
#define SP804_TIMER_CURRENT_REG 0x04
|
||||
#define SP804_TIMER_CONTROL_REG 0x08
|
||||
#define SP804_TIMER_INT_CLR_REG 0x0C
|
||||
#define SP804_TIMER_RAW_INT_STS_REG 0x10
|
||||
#define SP804_TIMER_MSK_INT_STS_REG 0x14
|
||||
#define SP804_TIMER_BG_LOAD_REG 0x18
|
||||
|
||||
// Timer control register bit definitions
|
||||
#define SP804_TIMER_CTRL_ONESHOT BIT0
|
||||
#define SP804_TIMER_CTRL_32BIT BIT1
|
||||
#define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)
|
||||
#define SP804_PRESCALE_DIV_1 0
|
||||
#define SP804_PRESCALE_DIV_16 BIT2
|
||||
#define SP804_PRESCALE_DIV_256 BIT3
|
||||
#define SP804_TIMER_CTRL_INT_ENABLE BIT5
|
||||
#define SP804_TIMER_CTRL_PERIODIC BIT6
|
||||
#define SP804_TIMER_CTRL_ENABLE BIT7
|
||||
|
||||
// Other SP804 Timer definitions
|
||||
#define SP804_MAX_TICKS 0xFFFFFFFF
|
||||
|
||||
// SP810 System Controller constants
|
||||
#define SP810_SYS_CTRL_REG 0x00
|
||||
#define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER0_EN BIT16
|
||||
#define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER1_EN BIT18
|
||||
#define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER2_EN BIT20
|
||||
#define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER3_EN BIT22
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
|
||||
#ifndef __SP805_WATCHDOG_H__
|
||||
#define __SP805_WATCHDOG_H__
|
||||
|
||||
// SP805 Watchdog Registers
|
||||
#define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)
|
||||
#define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)
|
||||
#define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)
|
||||
#define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)
|
||||
#define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)
|
||||
#define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)
|
||||
#define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)
|
||||
|
||||
#define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)
|
||||
#define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)
|
||||
#define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)
|
||||
#define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)
|
||||
|
||||
#define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)
|
||||
#define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)
|
||||
#define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)
|
||||
#define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)
|
||||
|
||||
// Timer control register bit definitions
|
||||
#define SP805_WDOG_CTRL_INTEN BIT0
|
||||
#define SP805_WDOG_CTRL_RESEN BIT1
|
||||
#define SP805_WDOG_RAW_INT_STS_WDOGRIS BIT0
|
||||
#define SP805_WDOG_MSK_INT_STS_WDOGMIS BIT0
|
||||
|
||||
#define SP805_WDOG_LOCK_IS_UNLOCKED 0x00000000
|
||||
#define SP805_WDOG_LOCK_IS_LOCKED 0x00000001
|
||||
#define SP805_WDOG_SPECIAL_UNLOCK_CODE 0x1ACCE551
|
||||
|
||||
#endif // __SP805_WATCHDOG_H__
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2014, ARM Ltd. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials are licensed and made available
|
||||
* under the terms and conditions of the BSD License which accompanies this
|
||||
* distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __BOOTMON_FS_FILE_INFO_H__
|
||||
#define __BOOTMON_FS_FILE_INFO_H__
|
||||
|
||||
#define BOOTMON_FS_FILE_INFO_ID \
|
||||
{ \
|
||||
0x41e26b9c, 0xada6, 0x45b3, {0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } \
|
||||
}
|
||||
|
||||
// From BootMonFS header file
|
||||
#define BOOTMONFS_IMAGE_DESCRIPTION_REGION_MAX 4
|
||||
|
||||
typedef struct {
|
||||
// The size of the structure.
|
||||
UINT64 Size;
|
||||
|
||||
// Subset of properties stored in the file meta-data.
|
||||
UINT32 EntryPoint;
|
||||
UINT32 RegionCount;
|
||||
struct {
|
||||
UINT32 LoadAddress;
|
||||
UINT32 Size;
|
||||
UINT32 Offset;
|
||||
UINT32 Checksum;
|
||||
} Region[BOOTMONFS_IMAGE_DESCRIPTION_REGION_MAX];
|
||||
|
||||
} BOOTMON_FS_FILE_INFO;
|
||||
|
||||
#define SIZE_OF_BOOTMON_FS_FILE_INFO \
|
||||
OFFSET_OF (BOOTMON_FS_FILE_INFO, Region[BOOTMONFS_IMAGE_DESCRIPTION_REGION_MAX - 1].Checksum)
|
||||
|
||||
extern EFI_GUID gArmBootMonFsFileInfoGuid;
|
||||
|
||||
#endif // __BOOTMON_FS_FILE_INFO_H__
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARMPLATFORMLIB_H_
|
||||
#define _ARMPLATFORMLIB_H_
|
||||
|
||||
//
|
||||
// The package level header files this module uses
|
||||
//
|
||||
#include <PiPei.h>
|
||||
//
|
||||
// The protocols, PPI and GUID defintions for this module
|
||||
//
|
||||
#include <Ppi/MasterBootMode.h>
|
||||
#include <Ppi/BootInRecoveryMode.h>
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
|
||||
/**
|
||||
This structure is used to describe a region of the EFI memory map
|
||||
|
||||
Every EFI regions of the system memory described by their physical start address and their size
|
||||
can have different attributes. Some regions can be tested and other untested.
|
||||
|
||||
**/
|
||||
typedef struct {
|
||||
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
|
||||
EFI_PHYSICAL_ADDRESS PhysicalStart;
|
||||
UINT64 NumberOfBytes;
|
||||
} ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR;
|
||||
|
||||
/**
|
||||
Return the core per cluster. The method may differ per core type
|
||||
|
||||
This function might be called from assembler before any stack is set.
|
||||
|
||||
@return Return the core count per cluster
|
||||
|
||||
**/
|
||||
UINTN
|
||||
ArmGetCpuCountPerCluster (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Return the core position from the value of its MpId register
|
||||
|
||||
This function returns the core position from the position 0 in the processor.
|
||||
This function might be called from assembler before any stack is set.
|
||||
|
||||
@return Return the core position
|
||||
|
||||
**/
|
||||
UINTN
|
||||
ArmPlatformGetCorePosition (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Return a non-zero value if the callee is the primary core
|
||||
|
||||
This function returns a non-zero value if the callee is the primary core.
|
||||
The primary core is the core responsible to initialize the hardware and run UEFI.
|
||||
This function might be called from assembler before any stack is set.
|
||||
|
||||
@return Return a non-zero value if the callee is the primary core.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
ArmPlatformIsPrimaryCore (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Return the MpId of the primary core
|
||||
|
||||
This function returns the MpId of the primary core.
|
||||
This function might be called from assembler before any stack is set.
|
||||
|
||||
@return Return the MpId of the primary core
|
||||
|
||||
**/
|
||||
UINTN
|
||||
ArmPlatformGetPrimaryCoreMpId (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Return the current Boot Mode
|
||||
|
||||
This function returns the boot reason on the platform
|
||||
|
||||
@return Return the current Boot Mode of the platform
|
||||
|
||||
**/
|
||||
EFI_BOOT_MODE
|
||||
ArmPlatformGetBootMode (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
First platform specific function to be called in the PEI phase
|
||||
|
||||
This function is actually the first function called by the PrePi
|
||||
or PrePeiCore modules. It allows to retrieve arguments passed to
|
||||
the UEFI firmware through the CPU registers.
|
||||
|
||||
This function might be written into assembler as no stack are set
|
||||
when the function is invoked.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformPeiBootAction (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize controllers that must setup in the normal world
|
||||
|
||||
This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
|
||||
in the PEI phase.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArmPlatformInitialize (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize the system (or sometimes called permanent) memory
|
||||
|
||||
This memory is generally represented by the DRAM.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformInitializeSystemMemory (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Return the Virtual Memory Map of your platform
|
||||
|
||||
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
|
||||
|
||||
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
|
||||
Virtual Memory mapping. This array must be ended by a zero-filled
|
||||
entry
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformGetVirtualMemoryMap (
|
||||
OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
|
||||
);
|
||||
|
||||
/**
|
||||
Return the Platform specific PPIs
|
||||
|
||||
This function exposes the Platform Specific PPIs. They can be used by any PrePi modules or passed
|
||||
to the PeiCore by PrePeiCore.
|
||||
|
||||
@param[out] PpiListSize Size in Bytes of the Platform PPI List
|
||||
@param[out] PpiList Platform PPI List
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformGetPlatformPpiList (
|
||||
OUT UINTN *PpiListSize,
|
||||
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARMPLATFORMSECLIB_H_
|
||||
#define _ARMPLATFORMSECLIB_H_
|
||||
|
||||
#define ARM_SEC_BOOT_MASK ~0
|
||||
#define ARM_SEC_COLD_BOOT (1 << 0)
|
||||
#define ARM_SEC_SECONDARY_COLD_BOOT (1 << 1)
|
||||
|
||||
/**
|
||||
Initialize the memory where the initial stacks will reside
|
||||
|
||||
This memory can contain the initial stacks (Secure and Secure Monitor stacks).
|
||||
In some platform, this region is already initialized and the implementation of this function can
|
||||
do nothing. This memory can also represent the Secure RAM.
|
||||
This function is called before the satck has been set up. Its implementation must ensure the stack
|
||||
pointer is not used (probably required to use assembly language)
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecBootMemoryInit (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Call at the beginning of the platform boot up
|
||||
|
||||
This function allows the firmware platform to do extra actions at the early
|
||||
stage of the platform power up.
|
||||
|
||||
Note: This function must be implemented in assembler as there is no stack set up yet
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecBootAction (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize controllers that must setup at the early stage
|
||||
|
||||
Some peripherals must be initialized in Secure World.
|
||||
For example: Some L2 controller, interconnect, clock, DMC, etc
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArmPlatformSecInitialize (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Call before jumping to Normal World
|
||||
|
||||
This function allows the firmware platform to do extra actions before
|
||||
jumping to the Normal World
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecExtraAction (
|
||||
IN UINTN MpId,
|
||||
OUT UINTN* JumpAddress
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize the Secure peripherals and memory regions
|
||||
|
||||
If Trustzone is supported by your platform then this function makes the required initialization
|
||||
of the secure peripherals and memory regions.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecTrustzoneInit (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/** @file ArmPlatformSysConfigLib.h
|
||||
|
||||
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __ARM_PLATFORM_SYS_CONFIG_H__
|
||||
#define __ARM_PLATFORM_SYS_CONFIG_H__
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
/* This header file makes it easier to access the System Configuration Registers
|
||||
* in the ARM Versatile Express motherboard.
|
||||
*/
|
||||
|
||||
//
|
||||
// Typedef
|
||||
//
|
||||
typedef UINT32 SYS_CONFIG_FUNCTION;
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigInitialize (
|
||||
VOID
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigGet (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
OUT UINT32* Value
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigGetValues (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINTN Size,
|
||||
OUT UINT32* Values
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigSet (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigSetDevice (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINT32 Device,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
#endif /* __SYS_CFG_REGISTERS_H__ */
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/** @file
|
||||
*
|
||||
* Definitions for the Dynamic Shell command library
|
||||
*
|
||||
* Copyright (C) 2014, ARM Ltd
|
||||
*
|
||||
* This program and the accompanying materials are licensed and made available
|
||||
* under the terms and conditions of the BSD License which accompanies this
|
||||
* distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARM_SHELL_CMD_LIB_H_
|
||||
#define _ARM_SHELL_CMD_LIB_H_
|
||||
|
||||
/**
|
||||
|
||||
Initialize and Install EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL for RunAxf command.
|
||||
|
||||
@param[in] ImageHandle Handle the protocol should be attached to.
|
||||
|
||||
@retval EFI_SUCCESS The command has been installed successfully.
|
||||
|
||||
@retval EFI_UNSUPPORTED Help for the command failed to initialise.
|
||||
|
||||
@return Status code returned by InstallProtocolInterface
|
||||
Boot Service function.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
ShellDynCmdRunAxfInstall (
|
||||
IN EFI_HANDLE ImageHandle
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
Uninstall the RunAxf Command
|
||||
|
||||
@param[in] ImageHandle Handle of the device where the protocol should have
|
||||
been installed.
|
||||
|
||||
@retval EFI_SUCCESS The device has been un-initialized successfully.
|
||||
|
||||
@return Status code returned by UninstallProtocolInterface
|
||||
Boot Service function.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
ShellDynCmdRunAxfUninstall (
|
||||
IN EFI_HANDLE ImageHandle
|
||||
);
|
||||
|
||||
#endif // _ARM_SHELL_CMD_LIB_H_
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/** @file
|
||||
* Main file supporting the Monitor World on ARM PLatforms
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARM_TRUSTED_MONITOR_LIB_H_
|
||||
#define __ARM_TRUSTED_MONITOR_LIB_H_
|
||||
|
||||
VOID
|
||||
ArmSecureMonitorWorldInitialize (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __LCDPLATFORMLIB_H
|
||||
#define __LCDPLATFORMLIB_H
|
||||
|
||||
#include <Protocol/GraphicsOutput.h>
|
||||
|
||||
#define LCD_VRAM_SIZE SIZE_8MB
|
||||
|
||||
//
|
||||
// Modes definitions
|
||||
//
|
||||
#define VGA 0
|
||||
#define SVGA 1
|
||||
#define XGA 2
|
||||
#define SXGA 3
|
||||
#define WSXGA 4
|
||||
#define UXGA 5
|
||||
#define HD 6
|
||||
|
||||
//
|
||||
// VGA Mode: 640 x 480
|
||||
//
|
||||
#define VGA_H_RES_PIXELS 640
|
||||
#define VGA_V_RES_PIXELS 480
|
||||
#define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */
|
||||
|
||||
#define VGA_H_SYNC ( 80 - 1)
|
||||
#define VGA_H_FRONT_PORCH ( 16 - 1)
|
||||
#define VGA_H_BACK_PORCH ( 64 - 1)
|
||||
|
||||
#define VGA_V_SYNC ( 4 - 1)
|
||||
#define VGA_V_FRONT_PORCH ( 3 - 1)
|
||||
#define VGA_V_BACK_PORCH ( 13 - 1)
|
||||
|
||||
//
|
||||
// SVGA Mode: 800 x 600
|
||||
//
|
||||
#define SVGA_H_RES_PIXELS 800
|
||||
#define SVGA_V_RES_PIXELS 600
|
||||
#define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */
|
||||
|
||||
#define SVGA_H_SYNC ( 80 - 1)
|
||||
#define SVGA_H_FRONT_PORCH ( 32 - 1)
|
||||
#define SVGA_H_BACK_PORCH (112 - 1)
|
||||
|
||||
#define SVGA_V_SYNC ( 4 - 1)
|
||||
#define SVGA_V_FRONT_PORCH ( 3 - 1)
|
||||
#define SVGA_V_BACK_PORCH ( 17 - 1)
|
||||
|
||||
//
|
||||
// XGA Mode: 1024 x 768
|
||||
//
|
||||
#define XGA_H_RES_PIXELS 1024
|
||||
#define XGA_V_RES_PIXELS 768
|
||||
#define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */
|
||||
|
||||
#define XGA_H_SYNC (104 - 1)
|
||||
#define XGA_H_FRONT_PORCH ( 48 - 1)
|
||||
#define XGA_H_BACK_PORCH (152 - 1)
|
||||
|
||||
#define XGA_V_SYNC ( 4 - 1)
|
||||
#define XGA_V_FRONT_PORCH ( 3 - 1)
|
||||
#define XGA_V_BACK_PORCH ( 23 - 1)
|
||||
|
||||
//
|
||||
// SXGA Mode: 1280 x 1024
|
||||
//
|
||||
#define SXGA_H_RES_PIXELS 1280
|
||||
#define SXGA_V_RES_PIXELS 1024
|
||||
#define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */
|
||||
|
||||
#define SXGA_H_SYNC (136 - 1)
|
||||
#define SXGA_H_FRONT_PORCH ( 80 - 1)
|
||||
#define SXGA_H_BACK_PORCH (216 - 1)
|
||||
|
||||
#define SXGA_V_SYNC ( 7 - 1)
|
||||
#define SXGA_V_FRONT_PORCH ( 3 - 1)
|
||||
#define SXGA_V_BACK_PORCH ( 29 - 1)
|
||||
|
||||
//
|
||||
// WSXGA+ Mode: 1680 x 1050
|
||||
//
|
||||
#define WSXGA_H_RES_PIXELS 1680
|
||||
#define WSXGA_V_RES_PIXELS 1050
|
||||
#define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */
|
||||
|
||||
#define WSXGA_H_SYNC (170 - 1)
|
||||
#define WSXGA_H_FRONT_PORCH (104 - 1)
|
||||
#define WSXGA_H_BACK_PORCH (274 - 1)
|
||||
|
||||
#define WSXGA_V_SYNC ( 5 - 1)
|
||||
#define WSXGA_V_FRONT_PORCH ( 4 - 1)
|
||||
#define WSXGA_V_BACK_PORCH ( 41 - 1)
|
||||
|
||||
//
|
||||
// UXGA Mode: 1600 x 1200
|
||||
//
|
||||
#define UXGA_H_RES_PIXELS 1600
|
||||
#define UXGA_V_RES_PIXELS 1200
|
||||
#define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */
|
||||
|
||||
#define UXGA_H_SYNC (168 - 1)
|
||||
#define UXGA_H_FRONT_PORCH (112 - 1)
|
||||
#define UXGA_H_BACK_PORCH (280 - 1)
|
||||
|
||||
#define UXGA_V_SYNC ( 4 - 1)
|
||||
#define UXGA_V_FRONT_PORCH ( 3 - 1)
|
||||
#define UXGA_V_BACK_PORCH ( 38 - 1)
|
||||
|
||||
//
|
||||
// HD Mode: 1920 x 1080
|
||||
//
|
||||
#define HD_H_RES_PIXELS 1920
|
||||
#define HD_V_RES_PIXELS 1080
|
||||
#define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */
|
||||
|
||||
#define HD_H_SYNC ( 79 - 1)
|
||||
#define HD_H_FRONT_PORCH (128 - 1)
|
||||
#define HD_H_BACK_PORCH (328 - 1)
|
||||
|
||||
#define HD_V_SYNC ( 5 - 1)
|
||||
#define HD_V_FRONT_PORCH ( 3 - 1)
|
||||
#define HD_V_BACK_PORCH ( 32 - 1)
|
||||
|
||||
//
|
||||
// Colour Masks
|
||||
//
|
||||
|
||||
#define LCD_24BPP_RED_MASK 0x00FF0000
|
||||
#define LCD_24BPP_GREEN_MASK 0x0000FF00
|
||||
#define LCD_24BPP_BLUE_MASK 0x000000FF
|
||||
#define LCD_24BPP_RESERVED_MASK 0xFF000000
|
||||
|
||||
#define LCD_16BPP_555_RED_MASK 0x00007C00
|
||||
#define LCD_16BPP_555_GREEN_MASK 0x000003E0
|
||||
#define LCD_16BPP_555_BLUE_MASK 0x0000001F
|
||||
#define LCD_16BPP_555_RESERVED_MASK 0x00000000
|
||||
|
||||
#define LCD_16BPP_565_RED_MASK 0x0000F800
|
||||
#define LCD_16BPP_565_GREEN_MASK 0x000007E0
|
||||
#define LCD_16BPP_565_BLUE_MASK 0x0000001F
|
||||
#define LCD_16BPP_565_RESERVED_MASK 0x00008000
|
||||
|
||||
#define LCD_12BPP_444_RED_MASK 0x00000F00
|
||||
#define LCD_12BPP_444_GREEN_MASK 0x000000F0
|
||||
#define LCD_12BPP_444_BLUE_MASK 0x0000000F
|
||||
#define LCD_12BPP_444_RESERVED_MASK 0x0000F000
|
||||
|
||||
|
||||
// The enumeration indexes maps the PL111 LcdBpp values used in the LCD Control Register
|
||||
typedef enum {
|
||||
LCD_BITS_PER_PIXEL_1 = 0,
|
||||
LCD_BITS_PER_PIXEL_2,
|
||||
LCD_BITS_PER_PIXEL_4,
|
||||
LCD_BITS_PER_PIXEL_8,
|
||||
LCD_BITS_PER_PIXEL_16_555,
|
||||
LCD_BITS_PER_PIXEL_24,
|
||||
LCD_BITS_PER_PIXEL_16_565,
|
||||
LCD_BITS_PER_PIXEL_12_444
|
||||
} LCD_BPP;
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformInitializeDisplay (
|
||||
IN EFI_HANDLE Handle
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformGetVram (
|
||||
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
|
||||
OUT UINTN* VramSize
|
||||
);
|
||||
|
||||
UINT32
|
||||
LcdPlatformGetMaxMode (
|
||||
VOID
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformSetMode (
|
||||
IN UINT32 ModeNumber
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformQueryMode (
|
||||
IN UINT32 ModeNumber,
|
||||
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformGetTimings (
|
||||
IN UINT32 ModeNumber,
|
||||
OUT UINT32* HRes,
|
||||
OUT UINT32* HSync,
|
||||
OUT UINT32* HBackPorch,
|
||||
OUT UINT32* HFrontPorch,
|
||||
OUT UINT32* VRes,
|
||||
OUT UINT32* VSync,
|
||||
OUT UINT32* VBackPorch,
|
||||
OUT UINT32* VFrontPorch
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformGetBpp (
|
||||
IN UINT32 ModeNumber,
|
||||
OUT LCD_BPP* Bpp
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _NORFLASHPLATFORMLIB_H_
|
||||
#define _NORFLASHPLATFORMLIB_H_
|
||||
|
||||
typedef struct {
|
||||
UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
|
||||
UINTN RegionBaseAddress; // Start address of one single region
|
||||
UINTN Size;
|
||||
UINTN BlockSize;
|
||||
EFI_GUID Guid;
|
||||
} NOR_FLASH_DESCRIPTION;
|
||||
|
||||
EFI_STATUS
|
||||
NorFlashPlatformInitialization (
|
||||
VOID
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
NorFlashPlatformGetDevices (
|
||||
OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions,
|
||||
OUT UINT32 *Count
|
||||
);
|
||||
|
||||
#endif /* _NORFLASHPLATFORMLIB_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue